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Wed, 18 Feb 2026 10:34:38 -0800 (PST) From: Jerome Brunet To: Ronald Claveau Cc: linux-amlogic@lists.infradead.org, Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 6/7] arm64: dts: amlogic: Add clock and EMMC for T7 In-Reply-To: <20260218112036.36905-1-linux-kernel-dev@aliel.fr> (Ronald Claveau's message of "Wed, 18 Feb 2026 12:20:33 +0100") References: <20260218101709.35450-1-linux-kernel-dev@aliel.fr> <20260218112036.36905-1-linux-kernel-dev@aliel.fr> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Wed, 18 Feb 2026 19:34:37 +0100 Message-ID: <1jecmh6gua.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On mer. 18 f=C3=A9vr. 2026 at 12:20, Ronald Claveau wrote: > Add fixed clock and EMMC support for Amlogic T7 SoC family dtsi. One topic per patch please > > Signed-off-by: Ronald Claveau > --- > arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 129 ++++++++++++++++++++ > 1 file changed, 129 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boo= t/dts/amlogic/amlogic-t7.dtsi > index 6510068bcff9..b84281e5cdd8 100644 > --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi > +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi > @@ -3,6 +3,8 @@ > * Copyright (c) 2019 Amlogic, Inc. All rights reserved. > */ >=20=20 > +#include > +#include > #include > #include > #include "amlogic-t7-reset.h" > @@ -224,6 +226,24 @@ apb4: bus@fe000000 { > #size-cells =3D <2>; > ranges =3D <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; >=20=20 > + clkc: clock-controller@0 { > + compatible =3D "amlogic,t7-peripherals-clkc"; > + reg =3D <0x0 0x0 0x0 0x49c>; > + #clock-cells =3D <1>; > + clocks =3D <&xtal>, > + <&fpll CLKID_FDIV2>, > + <&fpll CLKID_FDIV2P5>, > + <&fpll CLKID_FDIV3>, > + <&fpll CLKID_FDIV4>, > + <&fpll CLKID_FDIV5>, > + <&hifi_pll CLKID_HIFI_PLL>, > + <&mpll CLKID_MPLL2>, > + <&mpll CLKID_MPLL3>, > + <&gp0_pll CLKID_GP0_PLL>; > + clock-names =3D "xtal", "fdiv2", "fdiv2p5", "fdiv3", "fdiv4", > + "fdiv5", "hifi", "mpll2", "mpll3", "gp0"; > + }; > + > reset: reset-controller@2000 { > compatible =3D "amlogic,t7-reset"; > reg =3D <0x0 0x2000 0x0 0x98>; > @@ -250,6 +270,68 @@ gpio: bank@4000 { > #gpio-cells =3D <2>; > gpio-ranges =3D <&periphs_pinctrl 0 0 157>; > }; > + > + emmc_ctrl_pins: emmc-ctrl { > + mux-0 { > + groups =3D "emmc_cmd"; > + function =3D "emmc"; > + bias-pull-up; > + drive-strength-microamp =3D <4000>; > + }; > + > + mux-1 { > + groups =3D "emmc_clk"; > + function =3D "emmc"; > + bias-disable; > + drive-strength-microamp =3D <4000>; > + }; > + }; > + > + emmc_data_4b_pins: emmc-data-4b { > + mux-0 { > + groups =3D "emmc_nand_d0", > + "emmc_nand_d1", > + "emmc_nand_d2", > + "emmc_nand_d3"; > + function =3D "emmc"; > + bias-pull-up; > + drive-strength-microamp =3D <4000>; > + }; > + }; > + > + emmc_data_8b_pins: emmc-data-8b { > + mux-0 { > + groups =3D "emmc_nand_d0", > + "emmc_nand_d1", > + "emmc_nand_d2", > + "emmc_nand_d3", > + "emmc_nand_d4", > + "emmc_nand_d5", > + "emmc_nand_d6", > + "emmc_nand_d7"; > + function =3D "emmc"; > + bias-pull-up; > + drive-strength-microamp =3D <4000>; > + }; > + }; > + > + emmc_ds_pins: emmc-ds { > + mux { > + groups =3D "emmc_nand_ds"; > + function =3D "emmc"; > + bias-pull-down; > + drive-strength-microamp =3D <4000>; > + }; > + }; > + > + emmc_clk_gate_pins: emmc_clk_gate { > + mux { > + groups =3D "GPIOB_8"; > + function =3D "gpio_periphs"; > + bias-pull-down; > + drive-strength-microamp =3D <4000>; > + }; > + }; > }; >=20=20 > gpio_intc: interrupt-controller@4080 { > @@ -262,6 +344,38 @@ gpio_intc: interrupt-controller@4080 { > <10 11 12 13 14 15 16 17 18 19 20 21>; > }; >=20=20 > + fpll: clock-controller@8040 { > + compatible =3D "amlogic,t7-fpll"; > + reg =3D <0x0 0x8040 0x0 0x20>; > + #clock-cells =3D <1>; > + clocks =3D <&xtal>; > + clock-names =3D "xtal"; > + }; > + > + gp0_pll: clock-controller@8080 { > + compatible =3D "amlogic,t7-gp0-pll"; > + reg =3D <0x0 0x8080 0x0 0x20>; > + #clock-cells =3D <1>; > + clocks =3D <&xtal>; > + clock-names =3D "in0"; > + }; > + > + hifi_pll: clock-controller@8100 { > + compatible =3D "amlogic,t7-hifi-pll"; > + reg =3D <0x0 0x8100 0x0 0x20>; > + #clock-cells =3D <1>; > + clocks =3D <&xtal>; > + clock-names =3D "in0"; > + }; > + > + mpll: clock-controller@8180 { > + compatible =3D "amlogic,t7-mpll"; > + reg =3D <0x0 0x8180 0x0 0x20>; > + #clock-cells =3D <1>; > + clocks =3D <&fpll CLKID_FPLL_DCO>; > + clock-names =3D "in0"; > + }; > + > uart_a: serial@78000 { > compatible =3D "amlogic,t7-uart", "amlogic,meson-s4-uart"; > reg =3D <0x0 0x78000 0x0 0x18>; > @@ -276,6 +390,21 @@ sec_ao: ao-secure@10220 { > reg =3D <0x0 0x10220 0x0 0x140>; > amlogic,has-chip-id; > }; > + > + sd_emmc_c: mmc@8c000{ > + compatible =3D "amlogic,meson-axg-mmc"; > + reg =3D <0x0 0x8c000 0x0 0x800>; > + interrupts =3D ; > + status =3D "disabled"; > + clocks =3D <&clkc CLKID_SYS_SD_EMMC_C>, > + <&clkc CLKID_SD_EMMC_C>, > + <&gp0_pll CLKID_GP0_PLL>; > + clock-names =3D "core", "clkin0", "clkin1"; > + assigned-clocks =3D <&clkc CLKID_SD_EMMC_C_SEL>; > + assigned-clock-parents =3D <&xtal>; > + no-sdio; > + no-sd; > + }; > }; >=20=20 > }; --=20 Jerome