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Tue, 06 Jan 2026 02:25:21 -0800 (PST) From: Jerome Brunet To: Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, jian.hu@amlogic.com Subject: Re: [PATCH v1 0/3] clk: meson: small fixes for HDMI PLL OD In-Reply-To: <20260105204710.447779-1-martin.blumenstingl@googlemail.com> (Martin Blumenstingl's message of "Mon, 5 Jan 2026 21:47:07 +0100") References: <20260105204710.447779-1-martin.blumenstingl@googlemail.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Tue, 06 Jan 2026 11:25:20 +0100 Message-ID: <1jfr8jdomn.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On lun. 05 janv. 2026 at 21:47, Martin Blumenstingl wrote: > Hi Jerome, > > this series contains two fixes for preventing HDMI PLL OD /8 on > GXL/GXM and G12A/G12B/SM1, like the downstream driver does. See: > - downstream GXBB code: [0] > - downstream GXL/GXM code: [1] > - downstream G12A/G12B/SM1 code: [2] > > I have verified this on GXL (Le Potato) by setting HDMI PLL OD1 to 0x3 > (which should result in divide-by-8). The resulting frequency reported > by meson-clk-msr is double (meaning: only divide-by-4) compared to what > CCF sees. > > These are not critical for now since the CCF code-path for the HDMI PLL > is read-only (as drm/meson directly programs the registers). > > Additionally there's a cosmetic fix to use the HHI_HDMI_PLL_CNTL3 macro > instead of calculating HHI_HDMI_PLL_CNTL + 8. > > > [0] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c#L505-L627 > [1] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c#L501-L553 > [2] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c#L671-L721 > > > Martin Blumenstingl (3): > clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs > clk: meson: g12a: Limit the HDMI PLL OD to /4 > clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro Looks good. I'd like to add a comment like this in the code +/* + * GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4. + * A divider value of 3 should map to /8 but instead map /4 so ignore it. + */ (and a similar one for the G12). Is this Ok with you ? > > drivers/clk/meson/g12a.c | 13 ++++++++++--- > drivers/clk/meson/gxbb.c | 19 +++++++++++++------ > 2 files changed, 23 insertions(+), 9 deletions(-) -- Jerome