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Mon, 29 Sep 2025 01:48:06 -0700 (PDT) From: Jerome Brunet To: Martin Blumenstingl Cc: Chuan Liu , Michael Turquette , Stephen Boyd , Neil Armstrong , Kevin Hilman , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/2] clk: meson: Fix glitch free mux related issues In-Reply-To: (Martin Blumenstingl's message of "Sun, 28 Sep 2025 22:55:50 +0200") References: <20240929-fix_glitch_free-v1-0-22f9c36b7edf@amlogic.com> <20240929-fix_glitch_free-v1-2-22f9c36b7edf@amlogic.com> <20178015-4075-40e9-bbf4-20ae558c2bef@amlogic.com> <1jldyzrv2t.fsf@starbuckisacylon.baylibre.com> <9834c7c5-9334-4c78-a2fe-588ff03cf935@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Mon, 29 Sep 2025 10:48:05 +0200 Message-ID: <1jfrc563wa.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Sun 28 Sep 2025 at 22:55, Martin Blumenstingl wrote: > Hello, > > On Sun, Sep 28, 2025 at 8:41=E2=80=AFAM Chuan Liu = wrote: >> >> >> On 9/28/2025 2:05 PM, Chuan Liu wrote: >> > Hi Jerome & Martin: >> > >> > Sorry for the imprecise description of the glitch-free mux earlier. >> > >> > Recently, while troubleshooting a CPU hang issue caused by glitches, >> > I realized there was a discrepancy from our previous understanding, >> > so I'd like to clarify it here. > [...] >> An example of the clock waveform is shown below: >> >> 1 2 v v >> __ __ __ __ __ __ __ __ >> ori: =E2=86=91 |__=E2=86=91 |__=E2=86=91 |__=E2=86=91 |__=E2=86=91 = |__=E2=86=91 |__=E2=86=91 |__=E2=86=91 |__=E2=86=91 >> ^ >> 1 * cycle original channel. >> _ _ _ _ _ _ _ _ _ _ _ _ >> new: =E2=86=91 |_=E2=86=91 |_=E2=86=91 |_=E2=86=91 |_=E2=86=91 |_=E2=86= =91 |_=E2=86=91 |_=E2=86=91 |_=E2=86=91 |_=E2=86=91 |_=E2=86=91 |_=E2=86=91= |_=E2=86=91 >> ^ >> 5 * cycles new channel. >> __ __ _ _ _ _ >> out: =E2=86=91 |__=E2=86=91 |______________________=E2=86=91 |_=E2=86= =91 |_=E2=86=91 |_=E2=86=91 |_=E2=86=91 >> ^ ^ >> start switching mux. switch to new channel. Ok ... but when is it safe to disable the "ori" clock ? Can you do it at '1' already ? or do you have to wait for '2' ? > Thank you for the detailed report! > This is indeed problematic behavior. I guess the result is somewhat > random: depending on load (power draw), silicon lottery (quality), > temperature, voltage supply, ... - one may or may not see crashes > caused by this. > > Based on the previous discussion on this topic, my suggestion is to > split the original patch: > - one to add CLK_SET_RATE_GATE where needed (I think the meson8b.c > driver already has this where needed) to actually enable the > glitch-free mux behavior > - another one with the CLK_OPS_PARENT_ENABLE change (meson8b.c would > also need to be updated) to prevent the glitch-free mux from > temporarily outputting an electrical low signal. Jerome also asked to > document the behavior so we don't forget why we set this flag Yes please split the changes and visit all the controllers shipping this type of muxes. > > Both patches should get the proper "Fixes" tags. ... and proper fixes tag maybe different depending on the controller so there might more that just 2 changes. > I think it would also be great if you could include the waveform > example in at least the commit message as it helps understand the > problem. > > Let's also give Jerome some time to comment before you send patches. > > > Best regards, > Martin --=20 Jerome