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From: Jerome Brunet <jbrunet@baylibre.com>
To: "Yu-Chun Lin [林祐君]" <eleanor.lin@realtek.com>
Cc: "sboyd@kernel.org" <sboyd@kernel.org>,
	"bmasney+clk@redhat.com" <bmasney+clk@redhat.com>,
	"jbrunet+clk@baylibre.com" <jbrunet+clk@baylibre.com>,
	"robh@kernel.org" <robh@kernel.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"Edgar Lee [李承諭]" <cylee12@realtek.com>,
	"afaerber@suse.com" <afaerber@suse.com>,
	"Jyan Chou [周芷安]" <jyanchou@realtek.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-realtek-soc@lists.infradead.org"
	<linux-realtek-soc@lists.infradead.org>,
	"James Tai [戴志峰]" <james.tai@realtek.com>,
	"CY_Huang[黃鉦晏]" <cy.huang@realtek.com>,
	"Stanley Chang[昌育德]" <stanley_chang@realtek.com>,
	"Brian Masney" <bmasney@redhat.com>
Subject: RE: [PATCH v14 09/11] clk: realtek: Add RTD1625-CRT clock controller driver
Date: Fri, 25 Sep 2026 11:14:15 +0200	[thread overview]
Message-ID: <1jjyo98zh4.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <b9d5a1a82df34aadaee2390af871f7c8@realtek.com>

On mer. 23 sept. 2026 at 05:43, Yu-Chun Lin [林祐君] <eleanor.lin@realtek.com> wrote:

> Hi Jerome,
>
>> > +
>> > +static const char * const clk_gpu_parents[] = {"pll_gpu", "clk_sys"};
>> > +static RTK_CLK_REGMAP_MUX(clk_gpu, clk_gpu_parents,
>> CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
>> > +                       0x28, 12, 0x1); static const char * const
>> > +clk_ve_parents[] = {"pll_vo", "clk_sysh", "pll_ve1", "pll_ve2"};
>> > +static RTK_CLK_REGMAP_MUX(clk_ve1, clk_ve_parents,
>> CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
>> > +                       0x4c, 0, 0x3); static
>> > +RTK_CLK_REGMAP_MUX(clk_ve2, clk_ve_parents, CLK_SET_RATE_PARENT |
>> CLK_SET_RATE_NO_REPARENT,
>> > +                       0x4c, 3, 0x3); static
>> > +RTK_CLK_REGMAP_MUX(clk_ve4, clk_ve_parents, CLK_SET_RATE_PARENT |
>> CLK_SET_RATE_NO_REPARENT,
>> > +                       0x4c, 6, 0x3); static
>> > +RTK_CLK_REGMAP_GATE_NO_PARENT(clk_en_misc, CLK_IS_CRITICAL, 0x50,
>> 0,
>> > +1); clk_en_pcie0, 0, 0x50, 2,
>> > +1); clk_en_gspi, 0, 0x50, 6, 1);
>> > +clk_en_iso_misc, 0, 0x50, 10,
>> > +1); clk_en_sds, 0, 0x50, 12, 1);
>> > +clk_en_hdmi, 0, 0x50, 14, 1);
>> 
>> This is a lot of clock with no parents which is a bit suspicious especially for
>> gates.
>> What is really feeding those ?
>> 
>
> In v15, we will do our best to reduce the number of gate clocks without a parent.
>
> However, after discussing with our colleague, we confirmed that for some of
> these NO_PARENT gate clocks, their actual upstream clocks (like PLLs and
> Muxes) are located in separate, independent hardware subsystems. The registers
> controlling those upstream clocks are physically inaccessible from the Linux
> CPU domain.

Control and input are different things. It feels like your DT (binding)
description is not complete as it stands which will eventually be a problem.

A clock with no input is something that does generate the clock by
itself, like an osciallator. Pretending it has no parent because you
don't know how describe it yet is wrong.

>
> Best Regards,
> Yu-Chun

-- 
Jerome

  reply	other threads:[~2026-09-25  9:14 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-01  7:24 [PATCH v14 00/11] clk / reset: realtek: Add RTD1625 clock and reset support Yu-Chun Lin
2026-09-01  7:24 ` [PATCH v14 01/11] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin
2026-09-01  7:24 ` [PATCH v14 02/11] reset: Add Realtek basic reset support Yu-Chun Lin
2026-09-01  7:24 ` [PATCH v14 03/11] reset: realtek: Add RTD1625 reset controller driver Yu-Chun Lin
2026-09-01  7:24 ` [PATCH v14 04/11] clk: realtek: Introduce common probe() Yu-Chun Lin
2026-09-15 12:26   ` Jerome Brunet
2026-09-23  5:40     ` Yu-Chun Lin [林祐君]
2026-09-01  7:24 ` [PATCH v14 05/11] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin
2026-09-01  7:24 ` [PATCH v14 06/11] clk: realtek: Add support for gate clock Yu-Chun Lin
2026-09-15 12:42   ` Jerome Brunet
2026-09-23  5:41     ` Yu-Chun Lin [林祐君]
2026-09-01  7:24 ` [PATCH v14 07/11] clk: realtek: Add support for mux clock Yu-Chun Lin
2026-09-15 12:53   ` Jerome Brunet
2026-09-23  5:42     ` Yu-Chun Lin [林祐君]
2026-09-01  7:24 ` [PATCH v14 08/11] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin
2026-09-01  7:24 ` [PATCH v14 09/11] clk: realtek: Add RTD1625-CRT clock controller driver Yu-Chun Lin
2026-09-15 13:02   ` Jerome Brunet
2026-09-23  5:43     ` Yu-Chun Lin [林祐君]
2026-09-25  9:14       ` Jerome Brunet [this message]
2026-09-01  7:24 ` [PATCH v14 10/11] clk: realtek: Add RTD1625-ISO " Yu-Chun Lin
2026-09-01  7:24 ` [PATCH v14 11/11] arm64: dts: realtek: Add clock support for RTD1625 Yu-Chun Lin

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