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Wed, 18 Feb 2026 10:30:18 -0800 (PST) From: Jerome Brunet To: Ronald Claveau Cc: linux-amlogic@lists.infradead.org, Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/7] drivers: clk: meson: Add Amlogic T7 sys pll support In-Reply-To: <20260218110018.36348-1-linux-kernel-dev@aliel.fr> (Ronald Claveau's message of "Wed, 18 Feb 2026 12:00:15 +0100") References: <20260218101709.35450-1-linux-kernel-dev@aliel.fr> <20260218110018.36348-1-linux-kernel-dev@aliel.fr> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Wed, 18 Feb 2026 19:30:17 +0100 Message-ID: <1jjyw96h1i.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On mer. 18 f=C3=A9vr. 2026 at 12:00, Ronald Claveau wrote: > Add SYS PLL for the clock controller of the Amlogic T7 SoC family. Like the FDIVs, I think this is provided by SCMI. Check include/dt-bindings/clock/amlogic,t7-scmi.h > > Signed-off-by: Ronald Claveau > --- > drivers/clk/meson/t7-peripherals.c | 134 ++++++++++++++++++++++++++++- > 1 file changed, 131 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-pe= ripherals.c > index 214db7850d86..de206473f3a7 100644 > --- a/drivers/clk/meson/t7-peripherals.c > +++ b/drivers/clk/meson/t7-peripherals.c > @@ -176,6 +176,127 @@ static struct clk_regmap t7_rtc =3D { > }, > }; >=20=20 > +static u32 t7_sys_parents_val_table[] =3D { 0, 1, 2, 3, 4, 5, 7 }; > +static const struct clk_parent_data t7_sys_parents[] =3D { > + { .fw_name =3D "xtal", }, > + { .fw_name =3D "fdiv2", }, > + { .fw_name =3D "fdiv3", }, > + { .fw_name =3D "fdiv4", }, > + { .fw_name =3D "fdiv5", }, > + { .fw_name =3D "axi_clk_frcpu", }, > + { .hw =3D &t7_rtc.hw }, > +}; > + > +static struct clk_regmap t7_sys_a_sel =3D { > + .data =3D &(struct clk_regmap_mux_data){ > + .offset =3D SYS_CLK_CTRL0, > + .mask =3D 0x7, > + .shift =3D 10, > + .table =3D t7_sys_parents_val_table, > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "sys_a_sel", > + .ops =3D &clk_regmap_mux_ops, > + .parent_data =3D t7_sys_parents, > + .num_parents =3D ARRAY_SIZE(t7_sys_parents), > + }, > +}; > + > +static struct clk_regmap t7_sys_a_div =3D { > + .data =3D &(struct clk_regmap_div_data){ > + .offset =3D SYS_CLK_CTRL0, > + .shift =3D 0, > + .width =3D 10, > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "sys_a_div", > + .ops =3D &clk_regmap_divider_ops, > + .parent_hws =3D (const struct clk_hw *[]) { > + &t7_sys_a_sel.hw > + }, > + .num_parents =3D 1, > + .flags =3D CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_sys_a =3D { > + .data =3D &(struct clk_regmap_gate_data){ > + .offset =3D SYS_CLK_CTRL0, > + .bit_idx =3D 13, > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "sys_a", > + .ops =3D &clk_regmap_gate_ops, > + .parent_hws =3D (const struct clk_hw *[]) { > + &t7_sys_a_div.hw > + }, > + .num_parents =3D 1, > + }, > +}; > + > +static struct clk_regmap t7_sys_b_sel =3D { > + .data =3D &(struct clk_regmap_mux_data){ > + .offset =3D SYS_CLK_CTRL0, > + .mask =3D 0x7, > + .shift =3D 26, > + .table =3D t7_sys_parents_val_table, > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "sys_b_sel", > + .ops =3D &clk_regmap_mux_ops, > + .parent_data =3D t7_sys_parents, > + .num_parents =3D ARRAY_SIZE(t7_sys_parents), > + }, > +}; > + > +static struct clk_regmap t7_sys_b_div =3D { > + .data =3D &(struct clk_regmap_div_data){ > + .offset =3D SYS_CLK_CTRL0, > + .shift =3D 16, > + .width =3D 10, > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "sys_b_div", > + .ops =3D &clk_regmap_divider_ops, > + .parent_hws =3D (const struct clk_hw *[]) { > + &t7_sys_b_sel.hw > + }, > + .num_parents =3D 1, > + }, > +}; > + > +static struct clk_regmap t7_sys_b =3D { > + .data =3D &(struct clk_regmap_gate_data){ > + .offset =3D SYS_CLK_CTRL0, > + .bit_idx =3D 29, > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "sys_b", > + .ops =3D &clk_regmap_gate_ops, > + .parent_hws =3D (const struct clk_hw *[]) { > + &t7_sys_b_div.hw > + }, > + .num_parents =3D 1, > + }, > +}; > + > +static struct clk_regmap t7_sys =3D { > + .data =3D &(struct clk_regmap_mux_data){ > + .offset =3D SYS_CLK_CTRL0, > + .mask =3D 0x1, > + .shift =3D 15, > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "sys_clk", > + .ops =3D &clk_regmap_mux_ops, > + .parent_hws =3D (const struct clk_hw *[]) { > + &t7_sys_a.hw, > + &t7_sys_b.hw, > + }, > + .num_parents =3D 2, > + }, > +}; > + > static struct clk_regmap t7_ceca_dualdiv_in =3D { > .data =3D &(struct clk_regmap_gate_data){ > .offset =3D CECA_CTRL0, > @@ -824,7 +945,7 @@ static T7_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7, 0); >=20=20 > static const struct clk_parent_data t7_spicc_parents[] =3D { > { .fw_name =3D "xtal", }, > - { .fw_name =3D "sys", }, > + { .hw =3D &t7_sys.hw }, > { .fw_name =3D "fdiv4", }, > { .fw_name =3D "fdiv3", }, > { .fw_name =3D "fdiv2", }, > @@ -859,7 +980,7 @@ static T7_COMP_GATE(spicc5, SPICC_CLK_CTRL2, 22, 0); >=20=20 > static const struct clk_parent_data t7_saradc_parents[] =3D { > { .fw_name =3D "xtal" }, > - { .fw_name =3D "sys" }, > + { .hw =3D &t7_sys.hw }, > }; >=20=20 > static T7_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, t7_saradc_parents); > @@ -929,7 +1050,7 @@ static T7_COMP_SEL(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 25,= 0x3, t7_pwm_parents); > static T7_COMP_DIV(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 16, 8); > static T7_COMP_GATE(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 24, 0); >=20=20 > -static const struct clk_parent_data t7_sys_pclk_parents =3D { .fw_name = =3D "sys" }; > +static const struct clk_parent_data t7_sys_pclk_parents =3D { .hw =3D &t= 7_sys.hw }; >=20=20 > #define T7_SYS_PCLK(_name, _reg, _bit, _flags) \ > MESON_PCLK(t7_##_name, _reg, _bit, &t7_sys_pclk_parents, _flags) > @@ -1161,6 +1282,13 @@ static struct clk_hw *t7_peripherals_hw_clks[] =3D= { > [CLKID_PWM_AO_H_SEL] =3D &t7_pwm_ao_h_sel.hw, > [CLKID_PWM_AO_H_DIV] =3D &t7_pwm_ao_h_div.hw, > [CLKID_PWM_AO_H] =3D &t7_pwm_ao_h.hw, > + [CLKID_SYS_A_SEL] =3D &t7_sys_a_sel.hw, > + [CLKID_SYS_A_DIV] =3D &t7_sys_a_div.hw, > + [CLKID_SYS_A] =3D &t7_sys_a.hw, > + [CLKID_SYS_B_SEL] =3D &t7_sys_b_sel.hw, > + [CLKID_SYS_B_DIV] =3D &t7_sys_b_div.hw, > + [CLKID_SYS_B] =3D &t7_sys_b.hw, > + [CLKID_SYS] =3D &t7_sys.hw, > [CLKID_SYS_DDR] =3D &t7_sys_ddr.hw, > [CLKID_SYS_DOS] =3D &t7_sys_dos.hw, > [CLKID_SYS_MIPI_DSI_A] =3D &t7_sys_mipi_dsi_a.hw, --=20 Jerome