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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id u13-20020a05600c19cd00b003a2e1883a27sm6126778wmq.18.2022.07.28.02.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jul 2022 02:35:22 -0700 (PDT) References: <20220728054202.6981-1-yu.tu@amlogic.com> <20220728054202.6981-2-yu.tu@amlogic.com> <82e3fd36-df96-a555-4cea-47fabd26502b@linaro.org> <1jv8rhfw8h.fsf@starbuckisacylon.baylibre.com> <367cf98b-ef06-8f44-76c8-9099a1ec13dc@linaro.org> User-agent: mu4e 1.8.6; emacs 27.1 From: Jerome Brunet To: Krzysztof Kozlowski , Yu Tu , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Neil Armstrong , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl Subject: Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Date: Thu, 28 Jul 2022 11:09:52 +0200 In-reply-to: <367cf98b-ef06-8f44-76c8-9099a1ec13dc@linaro.org> Message-ID: <1jmtctfuli.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu 28 Jul 2022 at 11:02, Krzysztof Kozlowski wrote: > On 28/07/2022 10:50, Jerome Brunet wrote: >> >> On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski wrote: >> >>> On 28/07/2022 07:42, Yu Tu wrote: [...] >>>> +/* >>>> + * CLKID index values >>>> + */ >>>> + >>>> +#define CLKID_FIXED_PLL 1 >>>> +#define CLKID_FCLK_DIV2 3 >>>> +#define CLKID_FCLK_DIV3 5 >>>> +#define CLKID_FCLK_DIV4 7 >>>> +#define CLKID_FCLK_DIV5 9 >>>> +#define CLKID_FCLK_DIV7 11 >>> >>> Why these aren't continuous? IDs are expected to be incremented by 1. >>> >> >> All clocks have IDs, it is one big table in the driver, but we are not exposing them all. >> For example, with composite 'mux / div / gate' assembly, we usually need >> only the leaf. > > I understand you do not expose them all, but that is not the reason to > increment ID by 2 or 3... Otherwise these are not IDs and you are not > expected to put register offsets into the bindings (you do not bindings > in such case). Why is it not an IDs if it not continuous in the bindings ? If there is technical reason, we'll probably end up exposing everything. It would not be a dramatic change. I asked for this over v1 because we have done that is the past and I think it makes sense. I'm happy to be convinced to do things differently. Just looking for the technical reason that require contiuous exposed IDs. The other IDs exists, but we do not expose them as bindings. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/meson/gxbb.h#n125 > > >> Same has been done for the other AML controllers: >> For ex: >> >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h > > This cannot be fixed now, but it is very poor argument. Like saying "we > had a bug in other driver, so we implemented the bug here as well". I agree, "done before" is not a good argument. I was trying to provide a better picutre. I'm just surprised to have this new requirement that IDs have to be incremented by 1 (in the bindings) and I'd like to understand why what we had done could be considered a bug now. For example the simple-reset driver compute the reset offset from the IDs: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/reset/reset-simple.c There might be holes in the IDs if not all bits have reset maps. I don't think that would be a bug either. > > Best regards, > Krzysztof