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[82.65.169.74]) by smtp.gmail.com with ESMTPSA id c194sm8192606wme.46.2021.05.24.07.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 07:30:37 -0700 (PDT) References: <20210524134517.687089-1-martin.blumenstingl@googlemail.com> User-agent: mu4e 1.4.15; emacs 27.1 From: Jerome Brunet To: Martin Blumenstingl , linux-amlogic@lists.infradead.org Cc: narmstrong@baylibre.com, mturquette@baylibre.com, sboyd@kernel.org, khilman@baylibre.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel In-reply-to: <20210524134517.687089-1-martin.blumenstingl@googlemail.com> Message-ID: <1jmtskb3w2.fsf@starbuckisacylon.baylibre.com> Date: Mon, 24 May 2021 16:30:37 +0200 MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon 24 May 2021 at 15:45, Martin Blumenstingl wrote: > Use CLK_SET_RATE_NO_REPARENT for the vclk{,2}_in_sel clocks. The only > parent which is actually used is vid_pll_final_div. This should be set > using assigned-clock-parents in the .dts rather than removing some > "unwanted" clock parents from the clock driver. > > Suggested-by: Jerome Brunet > Signed-off-by: Martin Blumenstingl > --- > After a hint from Jerome (thanks) this is the improved version of > "clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel" from [0] > > > [0] https://patchwork.kernel.org/project/linux-clk/patch/20210524104533.555953-1-martin.blumenstingl@googlemail.com/ > > > drivers/clk/meson/meson8b.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > index a844d35b553a..0f8bd707217a 100644 > --- a/drivers/clk/meson/meson8b.c > +++ b/drivers/clk/meson/meson8b.c > @@ -1175,7 +1175,7 @@ static struct clk_regmap meson8b_vclk_in_sel = { > .ops = &clk_regmap_mux_ro_ops, I just noticed that these muxes are read-only ATM. It does not make this change (or the previous one) wrong but it does not make much sense as the mux won't ever change. I suppose you make this mutable with another patch later on ? > .parent_hws = meson8b_vclk_mux_parent_hws, > .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), > - .flags = CLK_SET_RATE_PARENT, > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > }, > }; > > @@ -1358,7 +1358,7 @@ static struct clk_regmap meson8b_vclk2_in_sel = { > .ops = &clk_regmap_mux_ro_ops, > .parent_hws = meson8b_vclk_mux_parent_hws, > .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), > - .flags = CLK_SET_RATE_PARENT, > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > }, > };