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Wed, 08 Jul 2026 05:38:09 -0700 (PDT) From: Jerome Brunet To: Chen-Yu Tsai Cc: Junhui Liu , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Maxime Ripard , linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 9/9] clk: sunxi-ng: sun6i-rtc: add a733 support In-Reply-To: (Chen-Yu Tsai's message of "Tue, 7 Jul 2026 00:47:30 +0800") References: <20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com> <20260706-a733-rtc-v4-9-f330728db3d3@baylibre.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Wed, 08 Jul 2026 14:38:08 +0200 Message-ID: <1jpl0xhd1r.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On mar. 07 juil. 2026 at 00:47, Chen-Yu Tsai wrote: >> + >> +static struct ccu_div osc24M_32k_div_a733_clk = { >> + .enable = BIT(1), >> + .div = _SUNXI_CCU_DIV_TABLE(14, 2, osc24M_32k_div_a733_table), >> + .common = { >> + .reg = DCXO_CTRL_REG, >> + .hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k-div", >> + osc24M, >> + &ccu_rodiv_ops, >> + 0), >> + }, >> +}; >> + >> +static SUNXI_CCU_GATE(osc24M_32k_clk, "osc24M-32k", "osc24M-32k-div", > > I'm not a big fan of using global clock parent names, especially when we > can have proper struct clk_hw pointer references. However in this case > it seems unavoidable without making a huge mess. > Indeed there is no way around it to support different SoC path with static data. >> + LOSC_OUT_GATING_REG, BIT(16), 0); >> >> static const struct clk_hw *rtc_32k_parents[] = { >> &osc32k_clk.common.hw, >> @@ -267,6 +296,15 @@ static struct ccu_mux osc32k_fanout_clk = { >> }, >> }; [...] >> }; >> MODULE_DEVICE_TABLE(of, sun6i_rtc_ccu_match); >> @@ -375,6 +435,13 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg) >> osc32k_fanout_init_data.parent_data = data->osc32k_fanout_parents; >> osc32k_fanout_init_data.num_parents = data->osc32k_fanout_nparents; >> >> + if (data->have_dcxo_status) >> + sun6i_rtc_ccu_hw_clks.hws[CLK_OSC24M_32K_DIV] = >> + &osc24M_32k_div_a733_clk.common.hw; >> + >> + if (!data->have_phy_ref_gates) >> + sun6i_rtc_ccu_hw_clks.num = CLK_OSC24M_32K_DIV + 1; > > Maybe keep the old CLK_NUMBER macro and call the new one CLK_NUMBER_A733? > The point is to not directly use a random macro + 1 here. Are you sure you about this ? You are going to end up with this CLK_NUMBER_A733 in the table which is going to be odd (unless I put an explanation next it) then this CLK_NUMBER without any suffix put next to clock gate things The choice I made initially was meant to keep thing as clear as possible * CLK_NUMBER remains the number of clock in the table * CLK_OSC24M_32K_DIV + 1 (while not very nice) clearly show which is the last clock in that case. It is not random IMO. If you still prefer the suggestion above, I'll submit v5 with it but it look odd to me. > > Otherwise, > > Reviewed-by: Chen-Yu Tsai > >> + >> return devm_sunxi_ccu_probe(dev, reg, &sun6i_rtc_ccu_desc); >> } >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h >> index ab7b92b47f59..4f4f4cb00f1d 100644 >> --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h >> +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h >> @@ -11,6 +11,6 @@ >> #define CLK_RTC_32K 6 >> #define CLK_OSC24M_32K_DIV 7 >> >> -#define CLK_NUMBER (CLK_OSC24M_32K_DIV + 1) >> +#define CLK_NUMBER (CLK_HOSC_SERDES1 + 1) >> >> #endif /* _CCU_SUN6I_RTC_H */ >> >> -- >> 2.47.3 >> -- Jerome