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[82.243.161.21]) by smtp.gmail.com with ESMTPSA id v188sm13242989wma.10.2019.12.09.00.32.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2019 00:32:19 -0800 (PST) References: <20191208210320.15539-1-repk@triplefau.lt> User-agent: mu4e 1.3.3; emacs 26.2 From: Jerome Brunet To: Remi Pommarel , Neil Armstrong , Kevin Hilman , Yue Wang Cc: Michael Turquette , Stephen Boyd , Lorenzo Pieralisi , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH 0/2] PCI: amlogic: Make PCIe working reliably on AXG platforms In-reply-to: <20191208210320.15539-1-repk@triplefau.lt> Date: Mon, 09 Dec 2019 09:32:18 +0100 Message-ID: <1jpngxew6l.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun 08 Dec 2019 at 22:03, Remi Pommarel wrote: > PCIe device probing failures have been seen on some AXG platforms and were > due to unreliable clock signal output. Setting HHI_MIPI_CNTL0[26] bit > solved the problem. After being contacted about this, vendor reported that > this bit was linked to PCIe PLL CML output. Thanks for reporting the problem. As Martin pointed out, the CML outputs already exist in the AXG clock controller but are handled using HHI_PCIE_PLL_CNTL6. Although incomplete, it seems to be aligned with the datasheet I have (v0.9) According to the same document, HHI_MIPI_CNTL0 belong to the MIPI Phy. Unfortunately bit 26 is not documented AFAICT, the clock controller is not appropriate driver to deal with this register/bit > > This serie adds a way to set this bit through AXG clock gating logic. > Platforms having this kind of issue could make use of this gating by > applying a patch to their devicetree similar to: > > clocks = <&clkc CLKID_USB > &clkc CLKID_MIPI_ENABLE > &clkc CLKID_PCIE_A > - &clkc CLKID_PCIE_CML_EN0>; > + &clkc CLKID_PCIE_CML_EN0 > + &clkc CLKID_PCIE_PLL_CML_ENABLE>; > clock-names = "pcie_general", > "pcie_mipi_en", > "pcie", > - "port"; > + "port", > + "pll_cml_en"; > resets = <&reset RESET_PCIE_PHY>, > <&reset RESET_PCIE_A>, > <&reset RESET_PCIE_APB>; A few remarks for your future patches: * You need to document any need binding you introduce: It means that there should have been a patch in Documentation/devicetree/... before using your newclock name in the pcie driver. As Martin pointed out, dt-bindings should be dealt with in their own patches > > > Remi Pommarel (2): > clk: meson: axg: add pcie pll cml gating Whenever possible, patches intended for different maintainers should be sent separately (different series) > PCI: amlogic: Use PCIe pll gate when available > > drivers/clk/meson/axg.c | 3 +++ > drivers/clk/meson/axg.h | 2 +- > drivers/pci/controller/dwc/pci-meson.c | 5 +++++ > include/dt-bindings/clock/axg-clkc.h | 1 + > 4 files changed, 10 insertions(+), 1 deletion(-)