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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de0ab5b03sm3925157f8f.30.2026.10.13.00.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 00:14:38 -0700 (PDT) From: Jerome Brunet To: Lucas Tanure , xianwei.zhao@amlogic.com, Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Andrew Lunn Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 8/8] dt-bindings: net: ethernet-controller: tabulate who adds the RGMII delays In-Reply-To: <20261010105900.247342-9-tanure@linux.com> References: <20261010105900.247342-1-tanure@linux.com> <20261010105900.247342-9-tanure@linux.com> Date: Tue, 13 Oct 2026 09:14:38 +0200 Message-ID: <1jqzhu9in5.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On sam. 10 oct. 2026 at 11:59, Lucas Tanure wrote: > The informative section explains in prose how phy-mode, the delay > properties in the MAC node and the mode handed to the PHY fit together, > and says itself that developers often get this wrong. A reader has to > work through several paragraphs before answering the one question they > usually have: for this phy-mode and these properties, which part adds > which delay. > > Add a table that answers it at a glance, with one row for every > combination the properties allow. > > Assisted-by: LLM > Signed-off-by: Lucas Tanure > --- > .../bindings/net/ethernet-controller.yaml | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml > index 1bafd687dcb1..bba27a9feb61 100644 > --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml > +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml > @@ -339,6 +339,24 @@ additionalProperties: true > # has added. Failure to remove the delay will result in a > # non-functioning link. > # > +# Put together, with the two properties in the MAC node, this is who > +# adds each delay: > +# > +# phy-mode tx-internal-delay-ps rx-internal-delay-ps TX delay RX delay > +# rgmii - - PCB trace PCB trace > +# rgmii-id - - PHY PHY > +# rgmii-id present - MAC PHY > +# rgmii-id - present PHY MAC > +# rgmii-id present present MAC MAC > +# rgmii-txid - - PHY PCB trace > +# rgmii-txid present - MAC PCB trace > +# rgmii-rxid - - PCB trace PHY > +# rgmii-rxid - present PCB trace MAC > +# That would match how the HW is working on the A733 Allwinner too but I'm not entirely sure this is what Andrew had in mind from our previous discussion [1]. Adding him to the thread [1]: https://lore.kernel.org/linux-sunxi/491f043e-6dc6-4936-a490-31a3362c5b6e@lunn.ch/ > +# A property for a clock the PCB already delays is not in this table. > +# It is either the fine tuning described next, or a mistake the MAC > +# should report as a fatal error. > +# > # Sometimes there is a need to fine tune the delays. Often the MAC or > # PHY can perform this fine tuning. In the MAC node, the Device Tree > # properties 'rx-internal-delay-ps' and 'tx-internal-delay-ps' should Acked-by: Jerome Brunet > -- > 2.56.0 > -- Jerome