From: Jerome Brunet <jbrunet@baylibre.com>
To: Troy Mitchell <troy.mitchell@linux.spacemit.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Yixun Lan <dlan@kernel.org>, Alex Elder <elder@riscstar.com>,
Inochi Amaoto <inochiama@outlook.com>,
Haylen Chu <heylenay@4d2.org>
Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
Troy Mitchell <troy.mitchell@linux.spacemit.com>
Subject: Re: [PATCH 0/5] clk: spacemit: preserve and safely synchronize firmware PLLs
Date: Fri, 25 Sep 2026 16:58:38 +0200 [thread overview]
Message-ID: <1jtsnd74yp.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20260909-spacemit-pll-init-v1-0-b3065ad5a4ac@linux.spacemit.com>
On mer. 09 sept. 2026 at 22:07, Troy Mitchell <troy.mitchell@linux.spacemit.com> wrote:
> Firmware may leave PLLs running with valid settings absent from Linux's
> rate tables. Replacing those settings during clock registration can
> stop CPUs that depend on them.
A provider should not act on the clock on its own.
>
> This series removes the init fallback to the first rate-table entry,
> decodes hardware rates directly and preserves unlisted rates. Opt-in
> synchronization applies only to differing parameters for the same
> decoded rate.
Don't think the provider should be responsible for that
> It temporarily moves mapped CPU consumers to validated
> PLL1 branches and restores their parents after the reprogrammed PLL
> locks.
This is typically a use case or policy choice that belong in whatever
consumes the clock. Your DVFS driver maybe ?
> PLL1 itself is not synchronized, and enabled outputs outside the
> managed CPU paths prevent synchronization.
>
> The series also corrects CPU divider and shared-parent modeling and
> makes MIX rate selection agree with programming. Runtime PLL rate
> changes still require a stopped PLL; automatic DVFS switching and new
> rate-table entries are outside this series.
>
> ---
> Troy Mitchell (5):
> clk: spacemit: derive PLL rates from hardware
> clk: spacemit: make MIX rate selection consistent
> clk: spacemit: describe CPU clock dividers and shared PLL muxes
> clk: spacemit: reject rate changes to running firmware PLLs
> clk: spacemit: safely synchronize PLL parameters during init
>
> drivers/clk/spacemit/ccu-k1.c | 60 +++--
> drivers/clk/spacemit/ccu-k3.c | 137 +++++++---
> drivers/clk/spacemit/ccu_common.c | 12 +
> drivers/clk/spacemit/ccu_common.h | 2 +
> drivers/clk/spacemit/ccu_mix.c | 35 ++-
> drivers/clk/spacemit/ccu_mix.h | 18 ++
> drivers/clk/spacemit/ccu_pll.c | 535 +++++++++++++++++++++++++++++++-------
> drivers/clk/spacemit/ccu_pll.h | 43 ++-
> 8 files changed, 689 insertions(+), 153 deletions(-)
> ---
> base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
> change-id: 20260907-spacemit-pll-init-c942bb249244
>
> Best regards,
> --
> Troy Mitchell <troy.mitchell@linux.spacemit.com>
>
--
Jerome
prev parent reply other threads:[~2026-09-25 14:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-09 14:07 Troy Mitchell
2026-09-09 14:07 ` [PATCH 1/5] clk: spacemit: derive PLL rates from hardware Troy Mitchell
2026-09-09 14:07 ` [PATCH 2/5] clk: spacemit: make MIX rate selection consistent Troy Mitchell
2026-09-10 13:01 ` Yao Zi
2026-09-10 14:19 ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 3/5] clk: spacemit: describe CPU clock dividers and shared PLL muxes Troy Mitchell
2026-09-09 14:07 ` [PATCH 4/5] clk: spacemit: reject rate changes to running firmware PLLs Troy Mitchell
2026-09-10 13:31 ` Yao Zi
2026-09-11 2:02 ` Troy Mitchell
2026-09-11 6:08 ` Yao Zi
2026-09-09 14:07 ` [PATCH 5/5] clk: spacemit: safely synchronize PLL parameters during init Troy Mitchell
2026-09-25 14:58 ` Jerome Brunet [this message]
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