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Tue, 23 Dec 2025 00:59:10 -0800 (PST) From: Jerome Brunet To: Chuan Liu via B4 Relay Cc: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 1/8] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support In-Reply-To: <20251028-a5-clk-v4-1-e62ca0aae243@amlogic.com> (Chuan Liu via's message of "Tue, 28 Oct 2025 17:52:27 +0800") References: <20251028-a5-clk-v4-0-e62ca0aae243@amlogic.com> <20251028-a5-clk-v4-1-e62ca0aae243@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Tue, 23 Dec 2025 09:59:05 +0100 Message-ID: <1jv7hx7ew6.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue 28 Oct 2025 at 17:52, Chuan Liu via B4 Relay wrote: > From: Chuan Liu > > Add the SCMI clock controller dt-bindings for the Amlogic A5 SoC > family. > > Signed-off-by: Chuan Liu > Reviewed-by: Rob Herring (Arm) > Signed-off-by: Xianwei Zhao Please read: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.19-rc1#n503 and adjust your patches accordingly > --- > include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h > new file mode 100644 > index 000000000000..1bf027d0110a > --- /dev/null > +++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h > @@ -0,0 +1,44 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ > +/* > + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. > + * Author: Chuan Liu > + */ > + > +#ifndef __AMLOGIC_A5_SCMI_CLKC_H > +#define __AMLOGIC_A5_SCMI_CLKC_H > + > +#define CLKID_OSC 0 > +#define CLKID_SYS_CLK 1 > +#define CLKID_AXI_CLK 2 > +#define CLKID_CPU_CLK 3 > +#define CLKID_DSU_CLK 4 > +#define CLKID_GP1_PLL 5 > +#define CLKID_FIXED_PLL_DCO 6 > +#define CLKID_FIXED_PLL 7 > +#define CLKID_ACLKM 8 > +#define CLKID_SYS_PLL_DIV16 9 > +#define CLKID_CPU_CLK_DIV16 10 > +#define CLKID_FCLK_50M_PREDIV 11 > +#define CLKID_FCLK_50M_DIV 12 > +#define CLKID_FCLK_50M 13 > +#define CLKID_FCLK_DIV2_DIV 14 > +#define CLKID_FCLK_DIV2 15 > +#define CLKID_FCLK_DIV2P5_DIV 16 > +#define CLKID_FCLK_DIV2P5 17 > +#define CLKID_FCLK_DIV3_DIV 18 > +#define CLKID_FCLK_DIV3 19 > +#define CLKID_FCLK_DIV4_DIV 20 > +#define CLKID_FCLK_DIV4 21 > +#define CLKID_FCLK_DIV5_DIV 22 > +#define CLKID_FCLK_DIV5 23 > +#define CLKID_FCLK_DIV7_DIV 24 > +#define CLKID_FCLK_DIV7 25 > +#define CLKID_SYS_MMC_PCLK 26 > +#define CLKID_SYS_CPU_CTRL 27 > +#define CLKID_SYS_IRQ_CTRL 28 > +#define CLKID_SYS_GIC 29 > +#define CLKID_SYS_BIG_NIC 30 > +#define CLKID_AXI_SYS_NIC 31 > +#define CLKID_AXI_CPU_DMC 32 > + > +#endif /* __AMLOGIC_A5_SCMI_CLKC_H */ -- Jerome