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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id y14-20020adffa4e000000b0021eb309c97dsm398706wrr.25.2022.07.28.02.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jul 2022 02:00:00 -0700 (PDT) References: <20220728054202.6981-1-yu.tu@amlogic.com> <20220728054202.6981-2-yu.tu@amlogic.com> <82e3fd36-df96-a555-4cea-47fabd26502b@linaro.org> User-agent: mu4e 1.8.6; emacs 27.1 From: Jerome Brunet To: Krzysztof Kozlowski , Yu Tu , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Neil Armstrong , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl Subject: Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Date: Thu, 28 Jul 2022 10:50:50 +0200 In-reply-to: <82e3fd36-df96-a555-4cea-47fabd26502b@linaro.org> Message-ID: <1jv8rhfw8h.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski wrote: > On 28/07/2022 07:42, Yu Tu wrote: >> Add new clock controller compatible and dt-bindings header for the >> Everything-Else domain of the S4 SoC. >> >> Signed-off-by: Yu Tu > > > >> diff --git a/MAINTAINERS b/MAINTAINERS >> index c1abc53f9e91..f872d0c0c253 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -1775,6 +1775,7 @@ F: Documentation/devicetree/bindings/clock/amlogic* >> F: drivers/clk/meson/ >> F: include/dt-bindings/clock/gxbb* >> F: include/dt-bindings/clock/meson* >> +F: include/dt-bindings/clock/s4-clkc.h >> >> ARM/Amlogic Meson SoC Crypto Drivers >> M: Corentin Labbe >> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h >> new file mode 100644 >> index 000000000000..b686c8877419 >> --- /dev/null >> +++ b/include/dt-bindings/clock/s4-clkc.h > > Filename with vendor prefix, so: > amlogic,s4-clkc.h > >> @@ -0,0 +1,146 @@ >> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ >> +/* >> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. >> + * Author: Yu Tu >> + */ >> + >> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H >> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H >> + >> +/* >> + * CLKID index values >> + */ >> + >> +#define CLKID_FIXED_PLL 1 >> +#define CLKID_FCLK_DIV2 3 >> +#define CLKID_FCLK_DIV3 5 >> +#define CLKID_FCLK_DIV4 7 >> +#define CLKID_FCLK_DIV5 9 >> +#define CLKID_FCLK_DIV7 11 > > Why these aren't continuous? IDs are expected to be incremented by 1. > All clocks have IDs, it is one big table in the driver, but we are not exposing them all. For example, with composite 'mux / div / gate' assembly, we usually need only the leaf. Same has been done for the other AML controllers: For ex: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h >> + >> +#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */ > > > Best regards, > Krzysztof