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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id b5sm1890075wmj.18.2019.10.09.05.04.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 05:04:42 -0700 (PDT) References: <20191007131649.1768-1-linux.amoon@gmail.com> <20191007131649.1768-6-linux.amoon@gmail.com> <7hsgo4cgeg.fsf@baylibre.com> User-agent: mu4e 1.3.3; emacs 26.2 From: Jerome Brunet To: Anand Moon , Martin Blumenstingl Cc: Kevin Hilman , Neil Armstrong , devicetree , linux-arm-kernel , linux-amlogic@lists.infradead.org, Linux Kernel Subject: Re: [RFCv1 5/5] arm64/ARM: configs: Change CONFIG_PWM_MESON from m to y In-reply-to: Date: Wed, 09 Oct 2019 14:04:41 +0200 Message-ID: <1jwode9lba.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 09 Oct 2019 at 10:48, Anand Moon wrote: > > Kernel command line: console=ttyAML0,115200n8 > root=PARTUUID=45d7d61e-01 rw rootwait > earlyprintk=serial,ttyAML0,115200 initcall_debug printk.time=y > > [0] https://pastebin.com/eBgJrSKe > >> you can also try the command line parameter "clk_ignore_unused" (it's >> just a gut feeling: maybe a "critical" clock is being disabled because >> it's not wired up correctly). >> > > It look like some clk issue after I added the *clk_ignore_unused* to > kernel command line > it booted further to login prompt and cpufreq DVFS seem to be loaded. > So I could conclude this is clk issue.below is the boot log > > Kernel command line: console=ttyAML0,115200n8 > root=PARTUUID=45d7d61e-01 rw rootwait > earlyprintk=serial,ttyAML0,115200 initcall_debug printk.time=y > clk_ignore_unused > > [1] https://pastebin.com/Nsk0wZQJ > Next step it to try narrow down the clock causing the issue. Remove clk_ignore_unused from the command line and add CLK_INGORE_UNUSED to the flag of some clocks your clock controller (g12a I think) until The peripheral clock gates already have this flag (something we should fix someday) so don't bother looking there. Most likely the source of the pwm is getting disabled between the late_init call and the probe of the PWM module. Since the pwm is already active (w/o a driver), gating the clock source shuts dowm the power to the cores. Looking a the possible inputs in pwm driver, I'd bet on fdiv4.