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Wed, 18 Feb 2026 10:09:06 -0800 (PST) From: Jerome Brunet To: Ronald Claveau Cc: linux-amlogic@lists.infradead.org, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/7] dt-bindings: clk: meson: Add Amlogic T7 fix pll support In-Reply-To: <20260218105611.36216-1-linux-kernel-dev@aliel.fr> (Ronald Claveau's message of "Wed, 18 Feb 2026 11:56:09 +0100") References: <20260218101709.35450-1-linux-kernel-dev@aliel.fr> <20260218105611.36216-1-linux-kernel-dev@aliel.fr> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Wed, 18 Feb 2026 19:09:05 +0100 Message-ID: <1jy0kp6i0u.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On mer. 18 f=C3=A9vr. 2026 at 11:56, Ronald Claveau wrote: > Add PLL for the clock controller of the Amlogic T7 SoC family. Usually bindings changes should comes before the driver changes in a series. This is especially important here because you are using the IDs in the driver. With order used here, bisect is broken. > > Signed-off-by: Ronald Claveau > --- > include/dt-bindings/clock/amlogic,t7-pll-clkc.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt= -bindings/clock/amlogic,t7-pll-clkc.h > index e2481f2f1163..690421009eab 100644 > --- a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h > +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h > @@ -53,4 +53,20 @@ > #define CLKID_MCLK_1_PRE 9 > #define CLKID_MCLK_1 10 >=20=20 > +/* ANALOG */ No idea what you mean with this ... > +#define CLKID_FPLL_DCO 0 > +#define CLKID_FPLL 1 > +#define CLKID_FDIV2_DIV 2 > +#define CLKID_FDIV2 3 > +#define CLKID_FDIV2P5_DIV 4 > +#define CLKID_FDIV2P5 5 > +#define CLKID_FDIV3_DIV 6 > +#define CLKID_FDIV3 7 > +#define CLKID_FDIV4_DIV 8 > +#define CLKID_FDIV4 9 > +#define CLKID_FDIV5_DIV 10 > +#define CLKID_FDIV5 11 > +#define CLKID_FDIV7_DIV 12 > +#define CLKID_FDIV7 13 > + > #endif /* __T7_PLL_CLKC_H */ --=20 Jerome