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Thu, 30 Oct 2025 01:41:08 -0700 (PDT) From: Jerome Brunet To: Chuan Liu via B4 Relay Cc: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , chuan.liu@amlogic.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, da@libre.computer Subject: Re: [PATCH v2 2/5] clk: amlogic: Improve the issue of PLL lock failures In-Reply-To: <20251030-optimize_pll_driver-v2-2-37273f5b25ab@amlogic.com> (Chuan Liu via's message of "Thu, 30 Oct 2025 13:24:12 +0800") References: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> <20251030-optimize_pll_driver-v2-2-37273f5b25ab@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Thu, 30 Oct 2025 09:41:07 +0100 Message-ID: <1jy0osye70.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Thu 30 Oct 2025 at 13:24, Chuan Liu via B4 Relay wrote: > From: Chuan Liu > > Due to factors such as temperature and process variations, the > internal circuits of the PLL may require a longer time to reach a > steady state, which can result in occasional lock failures on some > SoCs under low-temperature conditions. > > After enabling the PLL and releasing its reset, a 20 us delay is > added at each step to provide enough time for the internal PLL > circuit to stabilize, thus reducing the probability of PLL lock > failure. > > Signed-off-by: Chuan Liu > --- > drivers/clk/meson/clk-pll.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c > index 629f6af18ea1..f81ebf6cc981 100644 > --- a/drivers/clk/meson/clk-pll.c > +++ b/drivers/clk/meson/clk-pll.c > @@ -368,11 +368,16 @@ static int meson_clk_pll_enable(struct clk_hw *hw) > > /* Enable the pll */ > meson_parm_write(clk->map, &pll->en, 1); New line > + /* Wait for Bandgap and LDO to power up and stabilize */ > + udelay(20); > > /* Take the pll out reset */ > if (MESON_PARM_APPLICABLE(&pll->rst)) > meson_parm_write(clk->map, &pll->rst, 0); > > + /* Wait for PLL loop stabilization */ > + udelay(20); > + > /* > * Compared with the previous SoCs, self-adaption current module > * is newly added for A1, keep the new power-on sequence to enable the -- Jerome