From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9AD0C371053 for ; Mon, 1 Jun 2026 11:06:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780311995; cv=none; b=qd9w0coE9BrsCZS3y76d+hjO7y8M5x7MbT7WqfPwcgb2A2AKgUa1TEhEgZMgF40ylKEneU6lZ+m0wHmZCmNX7z+SV5sduauIkNqYJzJgR5zSkrrTGSH2DNuGv12XcobG7hQfwjuuh7HN4Ngl+DAJ9HGG1SmFHXjSROMPao8saCE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780311995; c=relaxed/simple; bh=rIPCRJlF3C5CGybciFVEHG8kM8P9Y/ochm5Nk/iXQLA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=lktMXs49NrTdUf83zUOO8w+Ne+4elvCNkszWYc2hwbs80IjHeIT0eTO3Tj1krVdmV5/FGTzFvV7T9K0z2LO7uPklu2kCErtexi3oyLnOgttyX0JcUvv/DoV4KsautRkKmJU2d7vvmRtnalNRVaTXRUo2h+l5gNOCtBXUtcSBoGM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=l6m577Xd; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="l6m577Xd" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 064561E7D; Mon, 1 Jun 2026 04:06:29 -0700 (PDT) Received: from [10.164.19.28] (unknown [10.164.19.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3E1123F632; Mon, 1 Jun 2026 04:06:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1780311993; bh=rIPCRJlF3C5CGybciFVEHG8kM8P9Y/ochm5Nk/iXQLA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=l6m577XdcFp83GD11AjZtBk9/x8HVwX6Ol04tR2Bdgz1+7hCiLXGiRbqT8axEXbFf kE9xwaZFqE+GQKddJq6yGwpqqS2+dXTVbFKMhcxwC5PZRCgArJ1h64IlrNE8PUE91X p06wQOo7mkNU7qeLlwGG1tCmc9n7PCivgQLkKbA0= Message-ID: <2000d7c9-3188-4539-ba9e-654d6460e21d@arm.com> Date: Mon, 1 Jun 2026 16:36:26 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC V2 13/14] arm64/mm: Add an abstraction level for tlbi_op To: Anshuman Khandual , linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Lorenzo Stoakes , Andrew Morton , David Hildenbrand , Mike Rapoport , Linu Cherian , Usama Arif , linux-kernel@vger.kernel.org, linux-mm@kvack.org References: <20260513044547.4128549-1-anshuman.khandual@arm.com> <20260513044547.4128549-14-anshuman.khandual@arm.com> Content-Language: en-US From: Dev Jain In-Reply-To: <20260513044547.4128549-14-anshuman.khandual@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 13/05/26 10:15 am, Anshuman Khandual wrote: > From: Linu Cherian > > With FEAT_D128, a new instruction aka TLBIP is being introduced for the TLB > range operations which has an argument size of 128 bit. > > Add an abstraction level to void (*tlbi_op)(u64 arg) helpers to support the > D128 variations when applicable. > > No functional changes are introduced with this patch. > > Signed-off-by: Linu Cherian > Signed-off-by: Anshuman Khandual > --- > arch/arm64/include/asm/tlbflush.h | 70 ++++++++++++++++--------------- > 1 file changed, 37 insertions(+), 33 deletions(-) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index c0bf5b398041..361d74ef8016 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -162,49 +162,53 @@ static inline void sme_dvmsync_batch(struct arch_tlbflush_unmap_batch *batch) > > #define TLBI_TTL_UNKNOWN INT_MAX > > -typedef void (*tlbi_op)(u64 arg); > +typedef u64 tlbi_args_t; > +#define __tlbi_wrapper(op, arg) __tlbi(op, arg) > +#define __tlbi_user_wrapper(op, arg) __tlbi_user(op, arg) The suffix "wrapper" sounds weird. How about "emit"? > > -static __always_inline void vae1is(u64 arg) > +typedef void (*tlbi_op)(tlbi_args_t arg); > + > +static __always_inline void vae1is(tlbi_args_t arg) > { > - __tlbi(vae1is, arg); > - __tlbi_user(vae1is, arg); > + __tlbi_wrapper(vae1is, arg); > + __tlbi_user_wrapper(vae1is, arg); > } > > -static __always_inline void vae2is(u64 arg) > +static __always_inline void vae2is(tlbi_args_t arg) > { > - __tlbi(vae2is, arg); > + __tlbi_wrapper(vae2is, arg); > } > > -static __always_inline void vale1(u64 arg) > +static __always_inline void vale1(tlbi_args_t arg) > { > - __tlbi(vale1, arg); > - __tlbi_user(vale1, arg); > + __tlbi_wrapper(vale1, arg); > + __tlbi_user_wrapper(vale1, arg); > } > > -static __always_inline void vale1is(u64 arg) > +static __always_inline void vale1is(tlbi_args_t arg) > { > - __tlbi(vale1is, arg); > - __tlbi_user(vale1is, arg); > + __tlbi_wrapper(vale1is, arg); > + __tlbi_user_wrapper(vale1is, arg); > } > > -static __always_inline void vale2is(u64 arg) > +static __always_inline void vale2is(tlbi_args_t arg) > { > - __tlbi(vale2is, arg); > + __tlbi_wrapper(vale2is, arg); > } > > -static __always_inline void vaale1is(u64 arg) > +static __always_inline void vaale1is(tlbi_args_t arg) > { > - __tlbi(vaale1is, arg); > + __tlbi_wrapper(vaale1is, arg); > } > > -static __always_inline void ipas2e1(u64 arg) > +static __always_inline void ipas2e1(tlbi_args_t arg) > { > - __tlbi(ipas2e1, arg); > + __tlbi_wrapper(ipas2e1, arg); > } > > -static __always_inline void ipas2e1is(u64 arg) > +static __always_inline void ipas2e1is(tlbi_args_t arg) > { > - __tlbi(ipas2e1is, arg); > + __tlbi_wrapper(ipas2e1is, arg); > } > > static __always_inline void __tlbi_level_asid(tlbi_op op, u64 addr, u32 level, > @@ -475,32 +479,32 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) > * operations can only span an even number of pages. We save this for last to > * ensure 64KB start alignment is maintained for the LPA2 case. > */ > -static __always_inline void rvae1is(u64 arg) > +static __always_inline void rvae1is(tlbi_args_t arg) > { > - __tlbi(rvae1is, arg); > - __tlbi_user(rvae1is, arg); > + __tlbi_wrapper(rvae1is, arg); > + __tlbi_user_wrapper(rvae1is, arg); > } > > -static __always_inline void rvale1(u64 arg) > +static __always_inline void rvale1(tlbi_args_t arg) > { > - __tlbi(rvale1, arg); > - __tlbi_user(rvale1, arg); > + __tlbi_wrapper(rvale1, arg); > + __tlbi_user_wrapper(rvale1, arg); > } > > -static __always_inline void rvale1is(u64 arg) > +static __always_inline void rvale1is(tlbi_args_t arg) > { > - __tlbi(rvale1is, arg); > - __tlbi_user(rvale1is, arg); > + __tlbi_wrapper(rvale1is, arg); > + __tlbi_user_wrapper(rvale1is, arg); > } > > -static __always_inline void rvaale1is(u64 arg) > +static __always_inline void rvaale1is(tlbi_args_t arg) > { > - __tlbi(rvaale1is, arg); > + __tlbi_wrapper(rvaale1is, arg); > } > > -static __always_inline void ripas2e1is(u64 arg) > +static __always_inline void ripas2e1is(tlbi_args_t arg) > { > - __tlbi(ripas2e1is, arg); > + __tlbi_wrapper(ripas2e1is, arg); > } > > static __always_inline void __tlbi_range(tlbi_op op, u64 addr,