Re: Data-corruption bug in VIA chipsets

[Ingo Oeser <ingo.oeser@informatik.tu-chemnitz.de>]

On Fri, Apr 13, 2001 at 10:00:32AM +0200, Dennis Bjorklund wrote:
> Here might be one of the resons for the trouble with VIA chipsets:
> 
> http://www.theregister.co.uk/content/3/18267.html
> 
> Some DMA error corrupting data, sounds like a really nasty bug. The
> information is minimal on that page.

These are the things, that one of the German links[1] suggest
(translated only, because I'm not the IDE guy ;-)):
   
   - PCI Delay Transaction = 0 (off) (Register 0x70, Bit 1)
   - PCI Master Read Caching = 0 (off) (Register 0x70, Bit 2)
   - PCI Latency = 0 (values between 0 and 32 *seem* to be safe,
        everything above seems to be *not* !)

Note: This also fixes some related USB issues according to [1].

Some hassles of setting the "PCI Latency" are described and one
of their reader found out, that it is "PCI Bus Master Time-Out"
on his board.

Register 0x75, Bits 0-3 are at 0001, which means 32 as latency
value. He set it to 0000 and it helps. This setting also does no
harm according to the magazine.

The observations are valid for the VT82C686B. One of their
readers also observed it at VT82C686A too and reported, that the
workaround helps.

So we might want to enable these workarounds for this
southbridge, too.

Hope this translation helps our maintainers a little ;-)

Regards

Ingo Oeser

[1] http://home.tiscalinet.de/au-ja/review-kt133a-4.html
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