From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id ; Sat, 5 May 2001 12:27:01 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id ; Sat, 5 May 2001 12:26:42 -0400 Received: from 4dyn183.delft.casema.net ([195.96.105.183]:44812 "EHLO abraracourcix.bitwizard.nl") by vger.kernel.org with ESMTP id ; Sat, 5 May 2001 12:26:32 -0400 Message-Id: <200105051626.SAA16651@cave.bitwizard.nl> Subject: Re: Athlon possible fixes In-Reply-To: from Alan Cox at "May 5, 2001 08:35:06 am" To: Alan Cox Date: Sat, 5 May 2001 18:26:30 +0200 (MEST) CC: linux-kernel@vger.kernel.org From: R.E.Wolff@BitWizard.nl (Rogier Wolff) X-Mailer: ELM [version 2.4ME+ PL60 (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org > + __asm__ __volatile__ ( > + " movq (%0), %%mm0\n" > + " movq 8(%0), %%mm1\n" > + " movq 16(%0), %%mm2\n" > + " movq 24(%0), %%mm3\n" > + " movq %%mm0, (%1)\n" > + " movq %%mm1, 8(%1)\n" > + " movq %%mm2, 16(%1)\n" > + " movq %%mm3, 24(%1)\n" > + " movq 32(%0), %%mm0\n" > + " movq 40(%0), %%mm1\n" > + " movq 48(%0), %%mm2\n" > + " movq 56(%0), %%mm3\n" > + " movq %%mm0, 32(%1)\n" > + " movq %%mm1, 40(%1)\n" > + " movq %%mm2, 48(%1)\n" > + " movq %%mm3, 56(%1)\n" > : : "r" (from), "r" (to) : "memory"); > from+=64; > to+=64; As all this is trying to avoid bus turnarounds (i.e. switching from reading to writing), wouldn't it be fastest to just trust that the CPU has at least 4k worth of cache? (and hope for the best that we don't get interrupted in the meanwhile). void copy_page (char *dest, char *source) { long *dst = (long *)dest, *src=(long *)source, *end= (long *)(source+PAGE_SIZE); #if 1 register int i; long t=0; static long tt; for (i=0;i