From: Mikael Pettersson <mikpe@csd.uu.se>
To: davej@suse.de
Cc: alan@lxorguk.ukuu.org.uk, linux-kernel@vger.kernel.org,
torvalds@transmeta.com
Subject: Re: [PATCH] Pentium IV cacheline size.
Date: Sat, 13 Oct 2001 16:17:14 +0200 (MET DST) [thread overview]
Message-ID: <200110131417.QAA25601@harpo.it.uu.se> (raw)
On Sat, 13 Oct 2001 12:57:33 +0100, Dave Jones wrote:
>Currently, we're using a L1_CACHE_SHIFT value of 7
>for Pentium 4, which equates to 128 byte cache lines.
>Curious, I dumped the info on the only P4 I could find,
>and noticed they were 64 byte.
>Upon checking the documentation, they're 64 byte there too.
>Is this just a thinko on someones part, or was there a
>rationale behind this that I've not realised ?
According to the P4 and Xeon optimisation manual (#248966-03), the
L1 cache has a 64-byte line size and the L2 cache has a 128-byte
line size. (Page 1-18, Table 1-1.) Perhaps someone just confused
the two, or the distinction wasn't known when the initial P4
support was added to the kernel.
/Mikael
next reply other threads:[~2001-10-13 14:17 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-10-13 14:17 Mikael Pettersson [this message]
2001-10-13 14:27 ` Dave Jones
-- strict thread matches above, loose matches on Subject: below --
2001-10-13 18:24 Manfred Spraul
2001-10-13 11:57 Dave Jones
2001-10-13 16:31 ` Mark Hahn
2001-10-13 17:34 ` Linus Torvalds
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