From: "David S. Miller" <davem@redhat.com>
To: torvalds@transmeta.com
Cc: viro@math.psu.edu, linux-kernel@vger.kernel.org
Subject: Re: oops in bk pull (oct 03)
Date: Fri, 04 Oct 2002 18:13:11 -0700 (PDT) [thread overview]
Message-ID: <20021004.181311.31550114.davem@redhat.com> (raw)
In-Reply-To: <Pine.LNX.4.44.0210041755310.2993-100000@home.transmeta.com>
From: Linus Torvalds <torvalds@transmeta.com>
Date: Fri, 4 Oct 2002 18:02:15 -0700 (PDT)
On Fri, 4 Oct 2002, Alexander Viro wrote:
> Hell knows. The only explanation I see (and that's not worth much) is that
> we somehow confuse the chipset and get crapped on something like next cache
> miss.
I don't see any better explanation right now, so I guess we just revert
that thing.
The people seeing this don't happen to be on Serverworks chipsets
are they?
I've seen a bug on serverworks where back to back PCI config
space operations can cause some to be lost or corrupted.
Another theory is that some device just dislikes being given
a 0 in one of it's base registers, but somehow ~0 is ok :-)
next prev parent reply other threads:[~2002-10-05 1:15 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-10-04 20:14 Paul E. Erkkila
2002-10-04 21:58 ` Linus Torvalds
2002-10-05 0:03 ` Paul E. Erkkila
2002-10-05 0:33 ` Alexander Viro
2002-10-05 0:40 ` Linus Torvalds
2002-10-05 0:51 ` Alexander Viro
2002-10-05 1:02 ` Linus Torvalds
2002-10-05 1:13 ` David S. Miller [this message]
2002-10-05 1:27 ` Alexander Viro
2002-10-05 1:41 ` Linus Torvalds
2002-10-05 2:00 ` David S. Miller
2002-10-05 2:22 ` Linus Torvalds
2002-10-05 2:22 ` David S. Miller
2002-10-05 2:00 ` Linus Torvalds
2002-10-05 3:20 ` Alexander Viro
2002-10-05 3:26 ` Linus Torvalds
2002-10-05 9:35 ` Ivan Kokshaysky
2002-10-05 1:14 ` Alexander Viro
2002-10-05 0:44 ` Alexander Viro
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