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Date: Thu, 20 Mar 2003 15:29:56 +0300
From: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
To: Dave Jones <davej@codemonkey.org.uk>, David Brownell <david-b@pacbell.net>,
       Jeff Garzik <jgarzik@pobox.com>, Greg KH <greg@kroah.com>,
       Russell King <rmk@arm.linux.org.uk>,
       Linus Torvalds <torvalds@transmeta.com>, linux-kernel@vger.kernel.org
Subject: Re: [patch 2.5] PCI MWI cacheline size fix
Message-ID: <20030320152956.A2584@jurassic.park.msu.ru>
References: <20030320135950.A2333@jurassic.park.msu.ru> <20030320115520.GB6995@suse.de>
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In-Reply-To: <20030320115520.GB6995@suse.de>; from davej@codemonkey.org.uk on Thu, Mar 20, 2003 at 11:55:20AM +0000
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On Thu, Mar 20, 2003 at 11:55:20AM +0000, Dave Jones wrote:
>  > +	else if (c->x86 > 6)
>  > +		pci_cache_line_size = 128 >> 2;	/* P4 */
>  >  
> 
> I'd feel more comfortable with this with a c->x86_vendor == X86_VENDOR_INTEL
> on the else if clause. The above code will silently break if for eg,
> VIA, Transmeta or any other clone manufacturer make a model 7 or higher CPU.

No, we'd just assume 128 bytes cache line size on such CPU, which is
safe unless it has cache lines larger than 128. But if we assume 32 bytes
while this new CPU has 64, MWI might corrupt memory by transferring
incomplete cache lines.

Ivan.