Re: cacheline size detection code in 2.5.66

[Ivan Kokshaysky <ink@jurassic.park.msu.ru>]

On Tue, Mar 25, 2003 at 08:15:32AM +0100, Andi Kleen wrote:
> This will be wrong on Pentium M for example which has a 32byte cache
> line but x86 model 9. But it's actually not needed, because all the 
> new CPUs report their cacheline size as part of CPUID for CLFLUSH.

We check x86 family, not model. According to Intel docs Pentium M
has family code 6.

> The x86-64 port extract it like this in setup.c:
> 	if (c->x86_capability[0] & (1<<19)) 
>        		c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
> 	}. 
> I changed its pci code to use that directly now. i386 likely
> should too. When no CLFLUSH is supported you can safely assume 32byte
> cachelines.

Apparently it's fine for K8, but what about Athlons? They have
bit 19 == 0 and 64-byte cache lines.
BTW, the "AMD Processor Recognition Application Note" calls bit 19
"Multiprocessing Capable". ;-)

Ivan.