From: Dave Jones <davej@codemonkey.org.uk>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Jamie Lokier <jamie@shareable.org>, Gerd Knorr <kraxel@suse.de>,
Linus Torvalds <torvalds@transmeta.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Andi Kleen <ak@suse.de>
Subject: Re: [patch] vesafb fix
Date: Tue, 15 Jul 2003 19:22:53 +0100 [thread overview]
Message-ID: <20030715182253.GG15505@suse.de> (raw)
In-Reply-To: <1058292400.3845.59.camel@dhcp22.swansea.linux.org.uk>
On Tue, Jul 15, 2003 at 07:06:41PM +0100, Alan Cox wrote:
> Not all the MTRR using chips use PAT - but its certainly a start.
Sure.
> The
> base algorithm for allocating MTRRs as efficiently as sanely possible
> is already in the kernel btw - or pretty close to it - its used by
> the Winchip code to cover RAM with out of order store.
Does that support wierdo cases like Jamie's though?
I can't see how you can cover an not-a-powerof2 size area of memory
without doing too little/too much. The winchip code was written with
RAM in mind, which is always a power of 2 unless you boot with
mem=fooMB
Dave
next prev parent reply other threads:[~2003-07-15 18:09 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-15 14:10 Gerd Knorr
2003-07-15 17:35 ` Jamie Lokier
2003-07-15 17:53 ` Dave Jones
2003-07-15 18:06 ` Alan Cox
2003-07-15 18:22 ` Dave Jones [this message]
2003-07-15 18:46 ` Alan Cox
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