Re: Simplification in pbus_size_mem

[Ivan Kokshaysky <ink@jurassic.park.msu.ru>]

On Thu, Nov 20, 2003 at 03:25:58PM +0000, Richard Curnow wrote:
>   Bus  1, device  11, function  0:
>     VGA compatible controller: SGS Thomson Microelectronics STG4000 [3D Prophet Kyro Series] (rev 1).
>       IRQ 2.
>       Master Capable.  Latency=32.  
>       Prefetchable 32 bit memory at 0x10000000 [0x13ffffff].
>       Prefetchable 32 bit memory at 0x14000000 [0x1407ffff].
>       I/O at 0x2000 [0x20ff].

Probably the second memory region is ROM - 'lspci -vvv' would clarify that.

> So is the idea that by rounding up 'size' to 96Mb in this case, it's
> guaranteed that there will be a 64Mb aligned chunk inside where the
> framebuffer can go, still leaving enough room around for the other
> allocation, _regardless_ of the alignment of the base of the memory
> aperture?  (Or if there are multiple PCI-to-PCI bridges, the aperture
> base for any one bridge is going to depend on the sizes of the apertures
> forwarded by the others, I suppose).

Exactly.

> > As a workaround, you can mark those additional 768Kb regions as
> > non-prefetchable and be done with it.
> 
> How do I do that?

Add a 'pcibios_fixup' routine for this platform, which does

	dev->resource[x].flags &= ~IORESOURCE_PREFETCH;

It can be either specific for that VGA controller (if it's built-in)
or for PCI devices with a class code of PCI_CLASS_DISPLAY_VGA or
(if that region is indeed a ROM) you can just mark ROM resources as
non-prefetchable for all PCI devices (i.e. x = PCI_ROM_RESOURCE).

Ivan.