PCI devices with no PCI_CACHE_LINE_SIZE implemented

[Matt Domsch <Matt_Domsch@dell.com>]

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Greg,

Some PCI device functions, such as the EHCI portion of Intel ICH5 and
ICH6 chips, do not implement the PCI_CACHE_LINE_SIZE register (which
is legal to not implement per PCI spec as it is a busmaster that
cannot issue a MWI).  However, for each of these, the kernel tries to
set the value, fails, and prints a KERN_WARNING message about it.

a) need this be a warning, wouldn't KERN_DEBUG suffice, if a message
is needed at all?  This is printed in pci_generic_prep_mwi().

b) How might you prefer to handle such devices?

Per the PCI 2.3 spec, reading a value of 0 may mean several things:
1) setting the register at all isn't supported
   - this is what pci.c assumes now and returns -EINVAL.
2) setting the register to the value you tried isn't supported, but
   you can try again with another value until you find the right one.
   - but there are no hints as to what the right value for a device
     might be.

Personally, I'd be happy if the printk were gone completely, but
that's your call.  With the prints there, our support organization is
concerned it can cause tech support calls for (in this case) a non-issue. 

Thanks,
Matt

-- 
Matt Domsch
Sr. Software Engineer, Lead Engineer
Dell Linux Solutions linux.dell.com & www.dell.com/linux
Linux on Dell mailing lists @ http://lists.us.dell.com

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