Re: perfctr questions

[bert hubert <ahu@ds9a.nl>]

On Fri, Jul 02, 2004 at 12:21:11PM +0200, Mikael Pettersson wrote:

> Should the kernel driver directly support some user-friendly
> model of the counters? No it should not, for several reasons:

We are in violent agreement - however, I do find that for a product to be
properly evaluated and to receive testing coverage, it is vital that the
learning curve not be this steep.

Right now, PAPI does not build for perfctr 2.7.3 (at least for me), nor do
Bryan's modifications. Furthermore, I had to reverse engineer a lot of
details to get my own things working.

I also read the AMD documentation and it is worthless and spends all of
three pages on the performance counters.

The good news however is that things do appear to work. What I'll do is whip
up a very small bootstrapping document. I'm sure PAPI is fine but for
many/my purposes it is overkill, I'd like for people to be able to
understand enough of perfctrs so they can start using them. 

Like this:

  CacheMeter cm;
  for(unsigned int n=0;n<iterations;++n) {
    c=area[(n*64)%limit];
    total+=c; // force gcc to actually look at it
  }
  cm.print();

Will do 100000000 reads over range of 10000000 bytes
Data cache accesses:	100109359
Data cache misses:	99977036
L2 hit, L1 miss:	26395
L2 miss, L1 miss:	1540114

Will do 100000000 reads over range of 1000 bytes
Data cache accesses:	100047618
Data cache misses:	8523
L2 hit, L1 miss:	0
L2 miss, L1 miss:	664

Code on htp://ds9a.nl/tmp/cmeter.cc - will only work on AMD and is in C++.

People with AMD knowledge are kindly invited to elaborate on the meaning of
'cache miss' v 'l2 and l2 miss' :-)

Mikael, thanks, this stuff is powerful and it will enable people to write
better code!

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