Re: [PATCH] Re: APIC/LAPIC hanging problems on nForce2 system.

[Andrew Morton <akpm@osdl.org>]

"Prakash K. Cheemplavam" <prakashkc@gmx.de> wrote:
>
> This patch applies the Nforce2 C1 halt disconnect fix, no matter if
> disconnect is enabled of not. I don't know whether checking the whole
> affected byte is necessary or the nibble would be enough (I am no Nvidia
> engineer).

The patch doesn't apply to the current tree.  Here's what we currently have:

static void __init pci_fixup_nforce2(struct pci_dev *dev)
{
	u32 val, fixed_val;
	u8 rev;

	pci_read_config_byte(dev, PCI_REVISION_ID, &rev);

	/*
	 * Chip  Old value   New value
	 * C17   0x1F0FFF01  0x1F01FF01
	 * C18D  0x9F0FFF01  0x9F01FF01
	 *
	 * Northbridge chip version may be determined by
	 * reading the PCI revision ID (0xC1 or greater is C18D).
	 */
	fixed_val = rev < 0xC1 ? 0x1F01FF01 : 0x9F01FF01;

	pci_read_config_dword(dev, 0x6c, &val);

	/*
	 * Apply fixup only if C1 Halt Disconnect is enabled
	 * (bit28) because it is not supported on some boards.
	 */
	if ((val & (1 << 28)) && val != fixed_val) {
		printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
		pci_write_config_dword(dev, 0x6c, fixed_val);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);

If you think this still needs fixing, please submit a new patch.  I think
we'd need to see a better explanation of the rationale for the change as
well, please.  What it does, why, how, etc.