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From: "Serge E. Hallyn" <serue@us.ibm.com>
To: Paul Mackerras <paulus@samba.org>
Cc: linux-kernel@vger.kernel.org, linuxppc64-dev@ozlabs.org
Subject: Re: prefetch on ppc64
Date: Wed, 30 Mar 2005 08:33:55 -0600	[thread overview]
Message-ID: <20050330143355.GA1692@IBM-BWN8ZTBWA01.austin.ibm.com> (raw)
In-Reply-To: <16970.9005.721117.942549@cargo.ozlabs.ibm.com>

Quoting Paul Mackerras (paulus@samba.org):
> Serge E. Hallyn writes:
> 
> > While investigating the inordinate performance impact one of my patches
> > seemed to be having, we tracked it down to two hlist_for_each_entry
> > loops, and finally to the prefetch instruction in the loop.
> 
> I would be interested to know what results you get if you leave the
> loops using hlist_for_each_entry but change prefetch() and prefetchw()
> to do the dcbt or dcbtst instruction only if the address is non-zero,
> like this:
> 
> static inline void prefetch(const void *x)
> {
> 	if (x)
> 	        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
> }
> 
> static inline void prefetchw(const void *x)
> {
> 	if (x)
> 	        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
> }
> 
> It seems that doing a prefetch on a NULL pointer, while it doesn't
> cause a fault, does waste time looking for a translation of the zero
> address.

Hi,

Olof Johansson had suggested that earlier, except that his patch used

if (unlikely(!x))
	return;

Performance was quite good, but not as good as having prefetch completely
disabled.  I got

# elements: 50, mean 851.263680, variance 24.561146, std dev 4.955920

compared to 860.823880 stdev 6.896914 with prefetch disabled.

thanks,
-serge


      parent reply	other threads:[~2005-03-30 14:34 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-03-30  3:40 Serge E. Hallyn
2005-03-30  3:55 ` Paul Mackerras
2005-03-30  5:38   ` Antonio Vargas
2005-03-30  6:00     ` Paul Mackerras
2005-03-30 14:33   ` Serge E. Hallyn [this message]

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