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From: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
To: Andi Kleen <ak@suse.de>
Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>,
	linux-kernel@vger.kernel.org, discuss@x86-64.org, akpm@osdl.org
Subject: Re: [Patch] x86, x86_64: Intel HT, Multi core detection code cleanup
Date: Thu, 6 Oct 2005 19:20:52 -0700	[thread overview]
Message-ID: <20051006192052.B21395@unix-os.sc.intel.com> (raw)
In-Reply-To: <200510061242.26563.ak@suse.de>; from ak@suse.de on Thu, Oct 06, 2005 at 12:42:25PM +0200

On Thu, Oct 06, 2005 at 12:42:25PM +0200, Andi Kleen wrote:
> On Thursday 06 October 2005 01:17, Siddha, Suresh B wrote:
> 
> > +
> > +#ifdef CONFIG_X86_HT
> > +#ifndef CONFIG_X86_64
> > +#include <mach_apic.h>
> > +#else
> > +#include <asm/mach_apic.h>
> > +#endif
> 
> Having such ifdefs is a clear cue that the code shouldn't be shared
> between architectures.

Andi, Those headers are for phys_pkg_id(). And its meaning is same on both 
x86 and x86_64(though its API is different. We can make it consistent across 
x86 and x86_64. But that will not solve the above pointed out ifdef hunk)

Unfortunately x86 mach specific vector implementation is not as simple as 
x86_64, resulting in the above ifdefs mess...

I can fix the API mess. Is there anything else you want me to do?

thanks,
suresh

  reply	other threads:[~2005-10-07  2:21 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-10-05 23:17 Siddha, Suresh B
2005-10-06 10:42 ` Andi Kleen
2005-10-07  2:20   ` Siddha, Suresh B [this message]
2005-10-07  9:52     ` [discuss] " Andi Kleen
2005-10-08  0:52       ` Siddha, Suresh B
2005-10-08 10:28         ` Andi Kleen
2005-10-12 21:30           ` Siddha, Suresh B
2005-10-12 21:36           ` [Patch 1/2] x86, x86_64: Intel HT, Multi core detection fixes Siddha, Suresh B
2005-10-12 21:49             ` [discuss] " Andi Kleen
2005-10-12 22:19               ` Siddha, Suresh B
2005-10-13  0:10                 ` Andi Kleen
2005-10-13 21:55                   ` Siddha, Suresh B
2005-10-13 21:59                   ` [Patch 2/2] x86, x86_64: fix Intel cache detection code assumption about threads sharing Siddha, Suresh B
2005-10-12 21:41           ` Siddha, Suresh B

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