From: Sam Ravnborg <sam@ravnborg.org>
To: Zach Brown <zach.brown@oracle.com>
Cc: Andi Kleen <ak@suse.de>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] [x86] align per-cpu section to configured cache bytes
Date: Sat, 28 Jan 2006 22:26:21 +0100 [thread overview]
Message-ID: <20060128212621.GA10548@mars.ravnborg.org> (raw)
In-Reply-To: <20060127220247.13917.8544.sendpatchset@tetsuo.zabbo.net>
On Fri, Jan 27, 2006 at 02:02:47PM -0800, Zach Brown wrote:
> [x86] align per-cpu section to configured cache bytes
>
> This matches the fix for a bug seen on x86-64. Test booted on old hardware
> that had 32 byte cachelines to begin with.
>
> Signed-off-by: Zach Brown <zach.brown@oracle.com>
I've applied this verbatim.
The asm-generic part suggested in other mail was not straightforward due
to subtle differences and I have not yet my cross compile environment
running on this box.
Sam
next prev parent reply other threads:[~2006-01-28 21:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-01-27 22:02 [PATCH 1/2] [x86-64] " Zach Brown
2006-01-27 22:02 ` [PATCH 2/2] [x86] " Zach Brown
2006-01-28 21:26 ` Sam Ravnborg [this message]
2006-01-27 23:32 ` [PATCH 1/2] [x86-64] " Sam Ravnborg
2006-01-27 23:45 ` Zach Brown
2006-01-28 3:03 ` Andi Kleen
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