From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965158AbWD1AZt (ORCPT ); Thu, 27 Apr 2006 20:25:49 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S965141AbWD1AZg (ORCPT ); Thu, 27 Apr 2006 20:25:36 -0400 Received: from cantor2.suse.de ([195.135.220.15]:21206 "EHLO mx2.suse.de") by vger.kernel.org with ESMTP id S965068AbWD1AZL (ORCPT ); Thu, 27 Apr 2006 20:25:11 -0400 Date: Thu, 27 Apr 2006 17:23:38 -0700 From: Greg KH To: linux-kernel@vger.kernel.org, stable@kernel.org Cc: Justin Forbes , Zwane Mwaikambo , "Theodore Ts'o" , Randy Dunlap , Dave Jones , Chuck Wolber , torvalds@osdl.org, akpm@osdl.org, alan@lxorguk.ukuu.org.uk, Atsushi Nemoto , Ralf Baechle , Greg Kroah-Hartman Subject: [patch 23/24] MIPS: Fix tx49_blast_icache32_page_indexed. Message-ID: <20060428002338.GX18750@kroah.com> References: <20060428001226.204293000@quad.kroah.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="MIPS-0003.patch" In-Reply-To: <20060428001557.GA18750@kroah.com> User-Agent: Mutt/1.5.11 Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org -stable review patch. If anyone has any objections, please let us know. ------------------ From: Atsushi Nemoto Fix the cache index value in tx49_blast_icache32_page_indexed(). This is damage by de62893bc0725f8b5f0445250577cd7a10b2d8f8 commit. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/mm/c-r4k.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) --- linux-2.6.16.11.orig/arch/mips/mm/c-r4k.c +++ linux-2.6.16.11/arch/mips/mm/c-r4k.c @@ -154,7 +154,8 @@ static inline void blast_icache32_r4600_ static inline void tx49_blast_icache32_page_indexed(unsigned long page) { - unsigned long start = page; + unsigned long indexmask = current_cpu_data.icache.waysize - 1; + unsigned long start = INDEX_BASE + (page & indexmask); unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << --