From: Chris Wright <chrisw@sous-sol.org>
To: Andi Kleen <ak@suse.de>
Cc: Chris Wright <chrisw@sous-sol.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
zach@vmware.com, torvalds@osdl.org
Subject: Re: [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
Date: Thu, 27 Apr 2006 23:27:04 -0700 [thread overview]
Message-ID: <20060428062704.GH2909@sorel.sous-sol.org> (raw)
In-Reply-To: <200604280808.44496.ak@suse.de>
* Andi Kleen (ak@suse.de) wrote:
> On Friday 28 April 2006 07:23, Chris Wright wrote:
> > * Andi Kleen (ak@suse.de) wrote:
> > > > +static inline void pmd_clear(pmd_t *pmd)
> > > > +{
> > > > + u32 *tmp = (u32 *)pmd;
> > > > + *tmp = 0;
> > > > + smp_wmb();
> > > > + *(tmp + 1) = 0;
> > > > +}
> > >
> > > I think that's still wrong - it should be wmb() not smp_wmb because this
> > > problem can happen on a UP kernel already.
> >
> > I thought the barrier is to keep compiler from reordering not processor.
>
> Yes, but with smp_wmb() it will go away on UP. And even on UP the
> CPU is free to speculate.
I must be confused. Doesn't that become a barrier() on UP?
next prev parent reply other threads:[~2006-04-28 6:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200604272001.k3RK1dmX007637@hera.kernel.org>
2006-04-28 5:18 ` Andi Kleen
2006-04-28 5:23 ` Chris Wright
2006-04-28 6:08 ` Andi Kleen
2006-04-28 6:27 ` Chris Wright [this message]
2006-04-28 6:29 ` Andi Kleen
2006-04-28 7:20 ` Nick Piggin
2006-04-28 14:54 ` Linus Torvalds
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