From: Stephane Eranian <eranian@hpl.hp.com>
To: Andi Kleen <ak@suse.de>
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86-64 add missing PMU MSR definitions
Date: Tue, 22 Aug 2006 03:34:58 -0700 [thread overview]
Message-ID: <20060822103458.GB30053@frankl.hpl.hp.com> (raw)
In-Reply-To: <200608210113.44984.ak@suse.de>
Andi,
On Mon, Aug 21, 2006 at 01:13:44AM +0200, Andi Kleen wrote:
> On Sunday 20 August 2006 23:48, Stephane Eranian wrote:
> > Hello,
> >
> > Here is a patch to add a couple of missing MSR definitions related
> > to Performance monitoring for EM64T. A separate patch contains the
> > i386 equivalent.
> >
> > Changelog:
> > - add MSR definitions for IA32_PEBS_ENABLE and PEBS_MATRIX_VERT
>
>
> The names seem somewhat mixed up.
>
> I think I would prefer P4 and no IA32 prefixes for all of them.
> (or does Core2 still have PEBS?)
OK, let's wait until Intel *finally* releases the Core 2 PMU specification
publicly and then I'll push a patch. Those MSRs are not that critical anyway.
Perfmon2 is probably the only consumer.
--
-Stephane
prev parent reply other threads:[~2006-08-22 10:45 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-08-20 21:48 Stephane Eranian
2006-08-20 23:13 ` Andi Kleen
2006-08-22 10:34 ` Stephane Eranian [this message]
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