From: Stephane Eranian <eranian@hpl.hp.com>
To: Andi Kleen <ak@suse.de>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>,
linux-kernel@vger.kernel.org, akpm@osdl.org
Subject: Re: [PATCH] i386 add Intel PEBS and BTS cpufeature bits and detection
Date: Fri, 17 Nov 2006 04:29:22 -0800 [thread overview]
Message-ID: <20061117122922.GE19907@frankl.hpl.hp.com> (raw)
In-Reply-To: <200611171022.20708.ak@suse.de>
On Fri, Nov 17, 2006 at 10:22:20AM +0100, Andi Kleen wrote:
> > The former
> > stores from/to information into MSRs and is very small (4 branches).
>
> P4 since Prescott has 16
>
Yes. I was talking about Core 2
> > On recent processors LBR and BTS can be constrained by priv level.
>
> Doesn't help for kernel debugging.
>
Well, if you set if for kernel level only, you do not capture user level
branches. This may happen if you crash soon after you've entered the kernel
and you have a small buffer.
--
-Stephane
next prev parent reply other threads:[~2006-11-17 12:29 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-11-15 21:32 Stephane Eranian
2006-11-15 21:34 ` [PATCH] x86-64 " Stephane Eranian
2006-11-16 0:18 ` [PATCH] i386 " Andrew Morton
2006-11-16 14:20 ` [PATCH] x86-64 add Intel BTS cpufeature bit and detection (take 2) Stephane Eranian
2006-11-16 14:22 ` [PATCH] i386 " Stephane Eranian
2006-11-16 14:23 ` [PATCH] x86-64 " Andi Kleen
2006-11-17 1:34 ` [PATCH] i386 add Intel PEBS and BTS cpufeature bits and detection Jeremy Fitzhardinge
2006-11-17 4:29 ` Andi Kleen
2006-11-17 7:57 ` Stephane Eranian
2006-11-17 9:22 ` Andi Kleen
2006-11-17 12:29 ` Stephane Eranian [this message]
2006-11-17 22:57 ` Jeremy Fitzhardinge
2006-11-18 8:24 ` Andi Kleen
2006-11-23 6:03 ` Keith Owens
2006-11-23 8:52 ` Andi Kleen
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