Re: exposing FSB clock speed in /sys

[lsorense@csclub.uwaterloo.ca (Lennart Sorensen)]

On Sat, Mar 31, 2007 at 12:18:32AM -0800, Stephane Eranian wrote:
> Well, I am talking about the bus that connects the processor socket to the
> chipset on Intel machines. On Intel Core 2 Duo (aka Woodcrest), you have 
> 2 sockets, thus two buses connecting to the chipset which then connects
> to the memory (among other things).
> 
> The Woodcrest (Intel Core PMU) is capable of measuring the number of bus
> transactions to memory (look at the BUS_* events). You can count per core
> or for the entire socket (both cores). In order to know if you saturate
> the bus (from socket to chipset), you need to know the theoretical peak
> number of transactions the bus can sustain. For that you need to bus
> frequency. 
> 
> I am not interested in older processors, but I think for all recent Intel
> processors, there is a fairly simple algorithm to get the frequency using
> a couple of MSRs (including MSR_IA32_EBL_CR_POWERON or MSR_FSB_FREQ).
> 
> Don't we already have /sys entries that exits only for certain processors
> or platforms?
> 
> I think the Opteron have HYPERTRANSPORT-related events which could be used
> to obtain similar metrics.
> 
> Knowledge of bus saturation is important for multi-core programming.

How about the speed between ram and the chipset?  Is it single or dual
channel?  Are there PCI devices currently doing DMA transfers to ram
taking up bandwidth?  What are the latencies of the ram, Etc, etc, etc.

And what could your software do differently if it knew this information?

--
Len Sorensen