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Date: Sun, 27 May 2007 22:18:02 -0600
From: Grant Grundler <grundler@parisc-linux.org>
To: Roland Dreier <rdreier@cisco.com>
Cc: David Miller <davem@davemloft.net>, abraham.manu@gmail.com, greg@kroah.com,
       linux-pci@atrey.karlin.mff.cuni.cz, linux-kernel@vger.kernel.org
Subject: Re: PCIE
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References: <46561287.8020103@gmail.com> <ada1wh560u1.fsf@cisco.com> <46584C30.4030206@gmail.com> <20070526.154910.78725926.davem@davemloft.net> <ada3b1h3gke.fsf@cisco.com>
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On Sun, May 27, 2007 at 06:03:29PM -0700, Roland Dreier wrote:
...
>  > I can imagine many systems where the cpu simply doesn't have enough
>  > interrupt pins to uniquely identify every possible MSI interrupt
>  > source.
> 
> I have a hard time imagining a PCI host bus controller that converts
> MSI interrupts back to wire interrupts that go to pins on the CPU.
> For one thing it would be hard to maintain the guarantee that
> MSI interrupts can't pass DMAs.

Whatever converts the MSI back to CPU IRQ pins would have to participate
in the "cache coherency domain". This would avoid issues around DMA ordering.
It _could_ be on the same silicon as the PCI Host bus controller as long
as the above is true.

> And it would be an absolutely silly architecture too.

While I agree it's silly, it might be cheaper if any patents are
involved, it reduces  complexity, power consumption or anything
else that costs time/money.

thanks,
grant