From: Arjan van de Ven <arjan@infradead.org>
To: Jan Engelhardt <jengelh@computergmbh.de>
Cc: Dennis Lubert <plasmahh@gmx.net>, linux-kernel@vger.kernel.org
Subject: Re: tsc timer related problems/questions
Date: Sun, 9 Sep 2007 19:31:48 +0100 [thread overview]
Message-ID: <20070909193148.6372dcc9@laptopd505.fenrus.org> (raw)
In-Reply-To: <Pine.LNX.4.64.0709092016120.11640@fbirervta.pbzchgretzou.qr>
On Sun, 9 Sep 2007 20:17:28 +0200 (CEST)
Jan Engelhardt <jengelh@computergmbh.de> wrote:
>
> On Sep 9 2007 17:49, Arjan van de Ven wrote:
> >>
> >> Question: Why are only Intel CPUs considered as stable? Could
> >> there be implemented a more sophisticated heuristic, that actually
> >> does some tests for tsc stability?
> >
> >on AMD multi-socket systems, afaik the tsc is not synchronized
> >between packages. On Intel the tsc is derived from the FSB which is
> >shared between the packages.
>
> Also, the TSC is not necessarily constant wrt. CPU clock speed.
> If your program stalls, the core may reduce frequency and hence
> TSC values are not linear to time anymore.
>
that depends on the CPU generation; most current cpus have
constant-rate tscs (at least constant wrt their own concept of time,
but at least independent of cpu frequency)...
it gets more iffy on idle; on deep idle the tsc tends to stop ;(
next prev parent reply other threads:[~2007-09-09 18:33 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-09 16:31 Dennis Lubert
2007-09-09 16:49 ` Arjan van de Ven
2007-09-09 18:17 ` Jan Engelhardt
2007-09-09 18:31 ` Arjan van de Ven [this message]
[not found] <fa.sr0PjjOVi2ceb88Wh7ND1s6urC0@ifi.uio.no>
2007-09-11 1:19 ` Robert Hancock
2007-09-11 18:54 ` Dennis Lubert
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