From: Nick Piggin <nickpiggin@yahoo.com.au>
To: Ingo Molnar <mingo@elte.hu>
Cc: linux-kernel@vger.kernel.org,
Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>
Subject: Re: what's up for v2.6.25 in x86.git
Date: Tue, 22 Jan 2008 12:28:21 +1100 [thread overview]
Message-ID: <200801221228.21404.nickpiggin@yahoo.com.au> (raw)
In-Reply-To: <200801221213.53490.nickpiggin@yahoo.com.au>
[-- Attachment #1: Type: text/plain, Size: 475 bytes --]
On Tuesday 22 January 2008 12:13, Nick Piggin wrote:
> On Tuesday 22 January 2008 07:14, Ingo Molnar wrote:
> > Nick Piggin (5):
> > mm: fix PageUptodate memory ordering bug
>
> This should actually be named differently. It should be
> called
>
> x86: don't unconditionally enable expensive SMP ppro workaround
>
> I actually had a more complete patch which printed a warning if
> booting such a system without the config option.
Ah sorry, here is a refreshed version
[-- Attachment #2: x86-no-ppro-fence.patch --]
[-- Type: text/x-diff, Size: 2849 bytes --]
The selection of many CPU architecture families causes pentium pro memory
ordering errata workarounds to be enabled. This causes memory barriers and
spinlocks to become much more expensive, just to provide a few hacks for a very
rare (nowadays) class of system.
Just print a warning if such a machine is detected. Also suggest a new CONFIG option that can be enabled to support such CPUs.
This saves nearly 1KB of icache in mm/ alone.
Signed-off-by: Nick Piggin <npiggin@suse.de>
---
Index: linux-2.6/arch/x86/Kconfig.cpu
===================================================================
--- linux-2.6.orig/arch/x86/Kconfig.cpu
+++ linux-2.6/arch/x86/Kconfig.cpu
@@ -322,9 +322,21 @@ config X86_XADD
default y
config X86_PPRO_FENCE
- bool
+ bool "PentiumPro memory ordering errata workaround"
depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
- default y
+ default n
+ help
+ Old PentiumPro multiprocessor systems had errata that could cause
+ memory operations to violate the x86 ordering standard in rare cases.
+ Enabling this option will attempt to work around some (but not all)
+ occurances of these problems, at the cost of much heavier spinlock
+ and memory barrier operations.
+
+ If you say N here, these systems will be detected and limited to a
+ single CPU at boot time.
+
+ If unsure, say N here. Even distro kernels should think twice before
+ enabling this: there are few systems, and an unlikely bug.
config X86_F00F_BUG
bool
Index: linux-2.6/arch/x86/kernel/cpu/intel.c
===================================================================
--- linux-2.6.orig/arch/x86/kernel/cpu/intel.c
+++ linux-2.6/arch/x86/kernel/cpu/intel.c
@@ -108,6 +108,32 @@ static void __cpuinit trap_init_f00f_bug
}
#endif
+/*
+ * Errata #66, #92, #51
+ */
+static void __cpuinit ppro_memory_bug(void)
+{
+#ifndef CONFIG_X86_PPRO_FENCE
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+ boot_cpu_data.x86 == 6 &&
+ boot_cpu_data.x86_model == 1) {
+ if (boot_cpu_data.x86_mask < 8)
+ printk(KERN_WARNING "WARNING: Pentium Pro with "
+ "Errata#66, #92, #51 detected. Running this kernel "
+ "may cause inconsistent results. "
+ "Enable CONFIG_X86_PPRO_FENCE.\n");
+
+#ifdef CONFIG_SMP
+ else
+ printk(KERN_WARNING "WARNING: Pentium Pro with "
+ "Errata#66, #92, #51 detected. Running this kernel "
+ "in an SMP system may cause inconsistent results. "
+ "Enable CONFIG_X86_PPRO_FENCE if using SMP system.\n");
+#endif
+ }
+#endif
+}
+
static void __cpuinit init_intel(struct cpuinfo_x86 *c)
{
unsigned int l2 = 0;
@@ -132,6 +158,8 @@ static void __cpuinit init_intel(struct
}
#endif
+ ppro_memory_bug();
+
select_idle_routine(c);
l2 = init_intel_cacheinfo(c);
if (c->cpuid_level > 9 ) {
next prev parent reply other threads:[~2008-01-22 1:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-01-21 20:14 Ingo Molnar
2008-01-22 1:13 ` Nick Piggin
2008-01-22 1:28 ` Nick Piggin [this message]
2008-01-22 12:39 ` Ingo Molnar
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