Re: [PATCH] x86 (64): make calibrate_APIC_clock() SMI-safe (take 3)

[Ingo Molnar <mingo@elte.hu>]

* Martin Wilck <martin.wilck@fujitsu-siemens.com> wrote:

> [PATCH] x86 (64): make calibrate_APIC_clock() SMI-safe (take 3)
> 
> Non-maskable asynchronous events (e.g. SMIs) which occur during the 
> APIC timer calibration can cause timer miscalibrations, sometimes by 
> large amounts. This patch fixes this by making sure that no 
> significant interruption occurs between APIC and TSC reads. SMIs may 
> still occur at some stage in the calibration loop, causing the loop to 
> last longer than intended. This doesn't matter though, as long as the 
> start and end values are both taken simultaneously.
> 
> Changed wrt take 2: Use max. possible start value for the APIC timer 
> to avoid underflow.
> 
> Signed-off-by: Martin Wilck <martin.wilck@fujitsu-siemens.com>
> Signed-off-by: Gerhard Wichert <gerhard.wichert@fujitsu-siemens.com>
> 
> --- arch/x86/kernel/apic_64.c	2008-07-25 15:39:51.000000000 +0200
> +++ arch/x86/kernel/apic_64.c.new	2008-07-25 15:55:08.000000000 +0200

nice - could you please implement it symmetrically on 32-bit APIC 
calibration as well?

	Ingo