Re: BUG: scheduling while atomic: ip/23212/0x00000102

[Jesse Barnes <jbarnes@virtuousgeek.org>]

On Monday, August 04, 2008 3:10 pm Rafael J. Wysocki wrote:
> > -	pci_read_config_word(tp->pdev,
> > -			     pm + PCI_PM_CTRL,
> > -			     &power_control);
> > -	power_control |= PCI_PM_CTRL_PME_STATUS;
> > -	power_control &= ~(PCI_PM_CTRL_STATE_MASK);
> >  	switch (state) {
> >  	case PCI_D0:
> > -		power_control |= 0;
> > -		pci_write_config_word(tp->pdev,
> > -				      pm + PCI_PM_CTRL,
> > -				      power_control);
> > -		udelay(100);	/* Delay after power state change */
> > +		pci_enable_wake(tp->pdev, state, false);
> > +		pci_set_power_state(tp->pdev, PCI_D0);
>
> Still, I don't think drivers should access the standard PCI PM registers
> directly, so perhaps there should be a version of pci_set_power_state()
> using udelay() instead of msleep() or we can just replace the msleep()
> in pci_set_power_state() with udelay()?

I think we should get rid of the open coded PCI PM state management, since 
otherwise platform related bugs like the Intel PCIe PM quirk that sets 
pci_pm_d3_delay to 120ms would have to be duplicated around the tree.

That said, waiting for 120ms with a busy wait seems a bit absurd if we can 
avoid it.  Either we need to find a way to make drivers only change states 
(which can be very slow) in non-atomic context or we'll need to add a busy 
wait variant of the power state call...

Jesse