Re: [stable] [PATCH 2.6.27-stable] Fix misreporting of #cores as #hyperthreads for Q9550

[Greg KH <greg@kroah.com>]

On Thu, Mar 19, 2009 at 01:27:44PM -0400, Joe Korty wrote:
> Fix misreporting of #cores for the Intel Quad Core Q9550.
> 
> [ for 2.6.27-stable ]
> 
> For the Q9550, in x86_64 mode, /proc/cpuinfo mistakenly
> reports the #cores present as the #hyperthreads present.
> i386 mode was not examined but is assumed to have the
> same problem.
> 
> A backport of the following three 2.6.29-rc1 patches
> fixes the problem:
> 
>   [PATCH] x86: unmask CPUID levels on Intel CPUs
>   [PATCH] x86: unmask CPUID levels on Intel CPUs, fix
>   [PATCH] x86: add MSR_IA32_MISC_ENABLE bits to <asm/msr-index.h>

Can you provide the git commit ids for these patches?

thanks,

greg k-h

> 
> From the first patch: "If the CPUID limit bit in
> MSR_IA32_MISC_ENABLE is set, clear it to make all CPUID
> information available.  This is required for some features
> to work, in particular XSAVE."
> 
> Originally-Developed-by: H. Peter Anvin <hpa@linux.intel.com>
> Backported-by: Joe Korty <joe.korty@ccur.com>
> Signed-off-by: Joe Korty <joe.korty@ccur.com>
> 
> Index: 2.6.27/include/asm-x86/msr-index.h
> ===================================================================
> --- 2.6.27.orig/include/asm-x86/msr-index.h	2009-03-19 11:07:59.000000000 -0400
> +++ 2.6.27/include/asm-x86/msr-index.h	2009-03-19 11:08:27.000000000 -0400
> @@ -196,6 +196,35 @@
>  #define MSR_IA32_THERM_STATUS		0x0000019c
>  #define MSR_IA32_MISC_ENABLE		0x000001a0
>  
> +/* MISC_ENABLE bits: architectural */
> +#define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)
> +#define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)
> +#define MSR_IA32_MISC_ENABLE_EMON		(1ULL << 7)
> +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL	(1ULL << 11)
> +#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL	(1ULL << 12)
> +#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP	(1ULL << 16)
> +#define MSR_IA32_MISC_ENABLE_MWAIT		(1ULL << 18)
> +#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID	(1ULL << 22)
> +#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE	(1ULL << 23)
> +#define MSR_IA32_MISC_ENABLE_XD_DISABLE		(1ULL << 34)
> +
> +/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
> +#define MSR_IA32_MISC_ENABLE_X87_COMPAT		(1ULL << 2)
> +#define MSR_IA32_MISC_ENABLE_TM1		(1ULL << 3)
> +#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE	(1ULL << 4)
> +#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE	(1ULL << 6)
> +#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK	(1ULL << 8)
> +#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE	(1ULL << 9)
> +#define MSR_IA32_MISC_ENABLE_FERR		(1ULL << 10)
> +#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX	(1ULL << 10)
> +#define MSR_IA32_MISC_ENABLE_TM2		(1ULL << 13)
> +#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE	(1ULL << 19)
> +#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK	(1ULL << 20)
> +#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT	(1ULL << 24)
> +#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE	(1ULL << 37)
> +#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE	(1ULL << 38)
> +#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE	(1ULL << 39)
> +
>  /* Intel Model 6 */
>  #define MSR_P6_EVNTSEL0			0x00000186
>  #define MSR_P6_EVNTSEL1			0x00000187
> Index: 2.6.27/arch/x86/kernel/cpu/intel.c
> ===================================================================
> --- 2.6.27.orig/arch/x86/kernel/cpu/intel.c	2009-03-19 11:08:26.000000000 -0400
> +++ 2.6.27/arch/x86/kernel/cpu/intel.c	2009-03-19 11:08:27.000000000 -0400
> @@ -32,6 +32,19 @@
>  
>  static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
>  {
> +	/* Unmask CPUID levels if masked: */
> +	if (c->x86 == 6 && c->x86_model >= 15) {
> +		u64 misc_enable;
> +
> +		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
> +
> +		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
> +			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
> +			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
> +			c->cpuid_level = cpuid_eax(0);
> +		}
> +	}
> +
>  	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
>  	if (c->x86 == 15 && c->x86_cache_alignment == 64)
>  		c->x86_cache_alignment = 128;
> Index: 2.6.27/arch/x86/kernel/cpu/intel_64.c
> ===================================================================
> --- 2.6.27.orig/arch/x86/kernel/cpu/intel_64.c	2009-03-19 11:08:26.000000000 -0400
> +++ 2.6.27/arch/x86/kernel/cpu/intel_64.c	2009-03-19 11:08:27.000000000 -0400
> @@ -9,6 +9,19 @@
>  
>  static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
>  {
> +	/* Unmask CPUID levels if masked: */
> +	if (c->x86 == 6 && c->x86_model >= 15) {
> +		u64 misc_enable;
> +
> +		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
> +
> +		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
> +			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
> +			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
> +			c->cpuid_level = cpuid_eax(0);
> +		}
> +	}
> +
>  	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
>  	    (c->x86 == 0x6 && c->x86_model >= 0x0e))
>  		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
> 
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