Re: [PATCH] ARM: copy_page.S: take into account the size of the cache line

[Russell King - ARM Linux <linux@arm.linux.org.uk>]

On Wed, Jul 15, 2009 at 04:12:19PM +0300, Siarhei Siamashka wrote:
> On Saturday 11 July 2009 02:51:23 ext Jamie Lokier wrote:
> > Kirill A. Shutemov wrote:
> > > From: Kirill A. Shutemov <kirill@shutemov.name>
> > >
> > > Optimized version of copy_page() was written with assumption that cache
> > > line size is 32 bytes. On Cortex-A8 cache line size is 64 bytes.
> > >
> > > This patch tries to generalize copy_page() to work with any cache line
> > > size if cache line size is multiple of 16 and page size is multiple of
> > > two cache line size.
> > >
> > > Unfortunately, kernel doesn't provide a macros with correct cache size.
> > > L1_CACHE_SHIFT is 5 on any ARM. So we have to define macros for this
> > > propose by ourself.
> >
> > Why don't you fix L1_CACHE_SHIFT for Cortex-A8?
> 
> That's the plan.

L1_CACHE_SHIFT is supposed to be a constant and the maximum cache line
shift for the processors in use.

Other functions (eg, dma_get_cache_alignment) can return either this or
the real cache line size.