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From: Ingo Molnar <mingo@elte.hu>
To: Johannes Stezenbach <js@sig21.net>
Cc: Robert Richter <robert.richter@amd.com>,
	Steven Rostedt <rostedt@goodmis.org>,
	Andi Kleen <andi@firstfloor.org>,
	x86@kernel.org, linux-kernel@vger.kernel.org,
	"Rafael J. Wysocki" <rjw@sisk.pl>
Subject: Re: 2.6.31-rc5 regression: x86 MCE malfunction on Thinkpad T42p
Date: Mon, 10 Aug 2009 23:31:33 +0200	[thread overview]
Message-ID: <20090810213133.GB16944@elte.hu> (raw)
In-Reply-To: <20090810203706.GA17338@sig21.net>


* Johannes Stezenbach <js@sig21.net> wrote:

> On Mon, Aug 10, 2009 at 10:14:06PM +0200, Ingo Molnar wrote:
> > * Johannes Stezenbach <js@sig21.net> wrote:
> > > 
> > > # ./perf stat true
> > > 
> > >  Performance counter stats for 'true':
> > > 
> > >        0.985808  task-clock-msecs         #      0.779 CPUs 
> > >               0  context-switches         #      0.000 M/sec
> > >               0  CPU-migrations           #      0.000 M/sec
> > >             110  page-faults              #      0.112 M/sec
> > >          583873  cycles                   #    592.279 M/sec
> > >          500937  instructions             #      0.858 IPC  
> > >   <not counted>  cache-references        
> > >   <not counted>  cache-misses            
> > > 
> > >     0.001265524  seconds time elapsed
> > 
> > That looks almost normal - except for cache-references and 
> > cache-misses that is not counted. Could you send the /proc/cpuinfo 
> > info please?
> 
> # cat /proc/cpuinfo 
> processor	: 0
> vendor_id	: GenuineIntel
> cpu family	: 6
> model		: 13
> model name	: Intel(R) Pentium(R) M processor 1.80GHz

ah, yes. There's no cache-references/misses, because in 
arch/x86/kernel/cpu/perf_counter.c we have two zero entries:

static const u64 p6_perfmon_event_map[] =
{
  [PERF_COUNT_HW_CPU_CYCLES]            = 0x0079,
  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0000, <----------
  [PERF_COUNT_HW_CACHE_MISSES]          = 0x0000, <----------
  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
  [PERF_COUNT_HW_BUS_CYCLES]            = 0x0062,
};

i.e. PERF_COUNT_HW_CACHE_REFERENCES and PERF_COUNT_HW_CACHE_MISSES 
is not filled in yet.

Could you try something like:

    perf stat -e r0f2e true

(0x2e: L2 requests, 0x0f: all units)

if i checked the docs right that counter would give us L2 cache 
stats - does it display non-zero values?

> stepping	: 6
> cpu MHz		: 600.000
> cache size	: 2048 KB
> fdiv_bug	: no
> hlt_bug		: no
> f00f_bug	: no
> coma_bug	: no
> fpu		: yes
> fpu_exception	: yes
> cpuid level	: 2
> wp		: yes
> flags		: fpu vme de pse tsc msr mce cx8 apic sep mtrr pge mca cmov clflush dts acpi mmx fxsr sse sse2 ss tm pbe bts est tm2
> bogomips	: 1196.15
> clflush size	: 64
> power management:
> 
> 
> > The warning is probably harmless - oprofile sampling still works 
> > fine, right?
> 
> I haven't done much testing so far, but so far it looks promising.
> 
> Could the warning be caused by the cpufreq ondemand governor? ISTR 
> that one should switch to the performance governor before doing 
> any profiling, but I forgot for this test.

there might be a connection - it could in theory cause sched_clock() 
transients and confuse the ring-buffer time-stamping.

	Ingo

  reply	other threads:[~2009-08-10 21:32 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-08-07 17:09 Johannes Stezenbach
2009-08-09 10:03 ` Johannes Stezenbach
2009-08-09 10:34   ` Bartlomiej Zolnierkiewicz
2009-08-09 16:47     ` Johannes Stezenbach
2009-08-10 10:31 ` Andi Kleen
2009-08-10 12:27   ` Johannes Stezenbach
2009-08-10 12:32     ` Andi Kleen
2009-08-10 12:56       ` Johannes Stezenbach
2009-08-10 13:29         ` Ingo Molnar
2009-08-10 19:26           ` Johannes Stezenbach
2009-08-10 19:44             ` Andi Kleen
2009-08-10 20:05               ` Robert Richter
2009-08-10 20:14             ` Ingo Molnar
2009-08-10 20:37               ` Johannes Stezenbach
2009-08-10 21:31                 ` Ingo Molnar [this message]
2009-08-10 22:13                   ` Johannes Stezenbach
2009-08-11  9:34                     ` [patch] cache-miss and cache-refs events on P6-mobile CPUs Ingo Molnar
2009-08-11  9:39                       ` Peter Zijlstra
2009-08-11 11:06                         ` Ingo Molnar
2009-08-11 11:21                           ` Peter Zijlstra
2009-08-11 15:50                       ` Johannes Stezenbach
2009-08-11 16:56                         ` Ingo Molnar
2009-08-11 15:40                     ` 2.6.31-rc5 regression: x86 MCE malfunction on Thinkpad T42p Johannes Stezenbach
2009-08-17 14:49                       ` Steven Rostedt
2009-08-12 11:59   ` *PING* [PATCH]: x86: mce: fix mce warning with disabled lapic Ingo Molnar

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