Re: Disabling DMA with ICH10?

[Alan Cox <alan@lxorguk.ukuu.org.uk>]

On Tue, 29 Sep 2009 22:35:54 +0200
Krzysztof Halasa <khc@pm.waw.pl> wrote:

> Alan Cox <alan@lxorguk.ukuu.org.uk> writes:
> 
> >> Not that long, there is no emulation there (except for port #80 (hex?)
> >> and similar). Normal 33 MHz access.
> >
> > ATA accesses go across the cable and while some of them are snooped,
> > cached and other magic is done there are cases it turns into a
> > transaction back and forth with the drive - that *is* slow. PIO 0 in fact
> > is ISA speed
> 
> Sure, PATA inserts wait states, the 4 bus cycles per access (or
> something like that) is the minimum for PIO on PCI. But it's still
> normal 33 MHz access (with as many wait states as the PATA mode needs),
> not ISA 8 MHz emulation (fastest PIO would be faster than ISA)

You are missing the point. The sequence is


INB foo

	CPU -> PCI device		read this register
	PCI device -> Disk
			trundle whirr whirrr
			clunk clunk thud
	Disk -> PCI device
	PCI device -> CPU... "5"

INB completes

The INB is not interruptible mid instruction and stalls the CPU for the
full period of the message passing back and forth across the bus. So PIO
0 on PCI stalls the bus for the equivalent of an ISA access, and PIO4
while a good deal faster is still a very long stall in hard real time
terms.