From: David Miller <davem@davemloft.net>
To: mathieu.desnoyers@polymtl.ca
Cc: nickpiggin@yahoo.com.au, linux-kernel@vger.kernel.org,
paulmck@linux.vnet.ibm.com
Subject: Re: sparc64 cmpxchg is not a full memory barrier anymore ?
Date: Thu, 22 Oct 2009 14:56:45 -0700 (PDT) [thread overview]
Message-ID: <20091022.145645.249762938.davem@davemloft.net> (raw)
In-Reply-To: <20091022183242.GA19307@Krystal>
From: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Date: Thu, 22 Oct 2009 14:32:42 -0400
> The same applies to the other atomic instructions we find in this list.
> How is the correct ordering of loads wrt to cmxchg (and other atomic
> ops) still ensured by this modification?
All actual sparc64 chips implement more strict ordering than
the V9 specification permits. The memory barriers were just
nops and actually not doing anything more than the chip
already does for us.
next prev parent reply other threads:[~2009-10-22 21:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-22 18:32 Mathieu Desnoyers
2009-10-22 19:57 ` Sparc64 support added to Userspace RCU Mathieu Desnoyers
2009-11-16 4:31 ` David Miller
2009-11-16 20:27 ` Mathieu Desnoyers
2009-10-22 21:56 ` David Miller [this message]
2009-10-23 12:33 ` sparc64 cmpxchg is not a full memory barrier anymore ? Mathieu Desnoyers
2009-10-23 14:19 ` David Miller
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