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Wed, 04 Nov 2026 23:13:05 -0800 (PST) Received: from [10.217.199.117] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b0b3160634sm2537144a91.6.2026.11.04.23.12.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Nov 2026 23:13:04 -0800 (PST) Message-ID: <200a8fe0-d1e2-454c-a40c-8f8caf0e53f4@oss.qualcomm.com> Date: Thu, 5 Nov 2026 12:42:56 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/6] dt-bindings: thermal: thermal-zones: add hardware-binning trip properties To: Krzysztof Kozlowski Cc: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Shuah Khan , Randy Dunlap , Amit Kucheria , Thara Gopinath , Bjorn Andersson , Konrad Dybcio , Abel Vesa , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Amit Kucheria References: <20261031-thermal_bin-v2-0-d76fd073ae98@oss.qualcomm.com> <20261031-thermal_bin-v2-1-d76fd073ae98@oss.qualcomm.com> <20261104-chivalrous-terrier-of-honor-9b3d2f@quoll> Content-Language: en-US From: Gaurav Kohli In-Reply-To: <20261104-chivalrous-terrier-of-honor-9b3d2f@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=EOGTQFZC c=1 sm=1 tr=0 ts=6aec2c82 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=1l-ioMR2BQVrcz0cqCEA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: 8KPftdsWQELlrx64MR6yAOEFG-_cGcIr X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA1MDAyOCBTYWx0ZWRfX1Up2IUY3/1I6 v/fPGozk3IWtXAorMW4CLQXMXaDQ16WDu8kW3rxHn6bWJDJqplqQnziHn9IHmwLAypJRNxQKxml mgV5Dq4Edy39S1zQ7GeTz2rzTccjWgE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA1MDAyOCBTYWx0ZWRfX0cWhz2GOjLc6 XW+KewO08AiekuJW+5DThLcaEfgc4Qab20SddkXcCV/5OgG4ImV5ZjbT2r7dXCKASwyLqO6oT2k 5KeBBD/awa2giE4/5JjTriOBkeFGuUj0KTZL+yc0Hakav0VXyvWaUf77NCh7fgSPPhe3/qX7j3u ajD7uTVa0Wu6S6G88rqKhsn8xjvHVHTsd4DMd6TQdtF8Ib2Bx+/8gJ14NleSCgUcsauIBIqKLd0 lio/3RmLVllTln2TR1w0tW07jZb7AGSCoaOjJ2JRVxrwrcVeMMQX6IvlN0NOS9XPdNTEYshyFwZ NVExHmCdPd8EUoDcGq5EWQSF6X7cSpGxYEBY/xrjVttTWQu5hgs/G7Vijzt0z3eFAylxPwQTHrK oxFPHr1VJqEs2RI6FqALa+WJzhO+AvbaTTuw+xn5RJnA8/9mMwoyIiPOYPPx9a/p+vtRXlyA6e7 47UeThr8CEUZimLvm9Q== X-Proofpoint-ORIG-GUID: 8KPftdsWQELlrx64MR6yAOEFG-_cGcIr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_02,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 suspectscore=0 bulkscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611050028 On 11/4/2026 6:13 PM, Krzysztof Kozlowski wrote: > On Sat, Oct 31, 2026 at 06:52:47PM +0530, Gaurav Kohli wrote: >> From: Amit Kucheria >> >> Differences in SoC packaging can be used to provide multiple SoC SKUs at >> different thermal and performance characteristics. The underlying SoC >> remains the same except for how much heat the packaging can dissipate, >> thereby influencing the critical trip point at which an SoC SKU needs to >> be throttled. This SKU-specific data is typically burned into fuses >> during manufacturing and can be read back at runtime. >> >> Add two optional trip-point properties to describe this: >> >> - 'temperature-bin': an array of per-bin trip temperatures, used >> instead of 'temperature' when the trip depends on the hardware >> revision encoded in fuses. >> >> - 'thermal-hw-bin': one or more bitmask groups describing the hardware >> revisions for which a trip point is valid, modeled on the >> 'opp-supported-hw' property of the OPP framework. >> >> Signed-off-by: Amit Kucheria >> Signed-off-by: Gaurav Kohli >> --- >> .../devicetree/bindings/thermal/thermal-zones.yaml | 57 +++++++++++++++++++++- >> 1 file changed, 56 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml >> index 999ad40a20d5..62590dfc77bf 100644 >> --- a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml >> +++ b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml >> @@ -152,6 +152,55 @@ patternProperties: >> situation where the trip gets constantly triggered soon after >> cooling action is removed. >> >> + temperature-bin: >> + $ref: /schemas/types.yaml#/definitions/int32-array >> + items: >> + minimum: -273000 >> + maximum: 200000 >> + description: | >> + An array of integers expressing trip temperatures in >> + millicelsius, one entry per hardware bin sub-group defined >> + in the thermal-hw-bin property. Each value is the trip >> + temperature for the corresponding hardware bin. >> + >> + Use this property instead of 'temperature' when the trip >> + temperature depends on the SoC hardware revision as encoded >> + in fuse values. The platform driver reads the fuse and >> + registers the hardware-version bitfields with the thermal >> + zone; the framework then selects the matching entry. >> + >> + Exactly one of 'temperature' or 'temperature-bin' must be >> + present in each trip node. >> + >> + thermal-hw-bin: >> + $ref: /schemas/types.yaml#/definitions/uint32-matrix >> + description: | >> + Optional bitmask(s) describing the hardware revisions for >> + which this trip point is valid. >> + >> + Uses the same format and semantics as the opp-supported-hw >> + property in the OPP framework. The platform provides N >> + 32-bit values describing the hardware it is running on. > > ', in a format specific to the thermal sensor provided in > "thermal-sensors" property.' > Thanks Krzysztof for the review. I will add minItems/maxItems for thermal-hw-bin and update the description to avoid tying it to the thermal-sensors provider. > This basically ties it to the thermal sensor which will disallow growing > the thermal-sensors to more than one phandle. The plural in > "thermal-sensors" name is confusing... > >> + Each trip node may provide one or more groups of N 32-bit >> + mask values. >> + >> + The total number of 32-bit cells must be a multiple of N. >> + Each contiguous group of N cells forms a sub-group. A >> + sub-group matches if, for all i in [0 .. N-1], the bitwise >> + AND of the i-th mask and the i-th platform hardware value >> + is non-zero. The trip point is enabled if any sub-group >> + matches. If multiple sub-groups match, the first matching >> + sub-group selects the corresponding temperature-bin entry. >> + >> + When used together with 'temperature-bin', the number of >> + sub-groups must equal the number of entries in >> + 'temperature-bin'. >> + >> + If absent, the trip point is valid for all hardware. > > minItems: 1 > maxItems: 32 > > Best regards, > Krzysztof