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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Alim Akhtar , Peter Griffin , =?UTF-8?Q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> <20260114-acpm-tmu-v1-3-cfe56d93e90f@linaro.org> <20260115-slim-denim-potoo-cad9cb@quoll> Content-Language: en-US From: Tudor Ambarus In-Reply-To: <20260115-slim-denim-potoo-cad9cb@quoll> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/15/26 3:36 PM, Krzysztof Kozlowski wrote: > On Wed, Jan 14, 2026 at 02:16:31PM +0000, Tudor Ambarus wrote: >> Document the bindings for the Thermal Management Unit (TMU) System >> Controller found on Google GS101 SoCs. >> >> This memory-mapped block exposes the registers required for reading >> thermal interrupt status bits. It functions as a syscon provider, > > I don't think this is syscon, but the actual TMU. Syscon is various, > unrelated system configuration registers. > >> allowing the main thermal driver to access these registers while >> the firmware manages the core thermal logic. >> >> Signed-off-by: Tudor Ambarus >> --- >> .../bindings/mfd/google,gs101-tmu-syscon.yaml | 37 ++++++++++++++++++++++ >> 1 file changed, 37 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/mfd/google,gs101-tmu-syscon.yaml b/Documentation/devicetree/bindings/mfd/google,gs101-tmu-syscon.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..6a11e43abeaa23ee473be2153478436856277714 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mfd/google,gs101-tmu-syscon.yaml > > Not MFD either, but soc. You are right, it's not a syscon, it's just a normal thermal IP block from which I need to access the interrupt pending registers. Then I guess I shall describe the new binding in bindings/thermal/, please correct me if I'm wrong. > >> @@ -0,0 +1,37 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mfd/google,gs101-tmu-syscon.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Google GS101 TMU System Controller >> + >> +maintainers: >> + - Tudor Ambarus >> + >> +description: | > > Drop | > >> + The TMU System Controller provides a memory-mapped interface for >> + accessing the interrupt status registers of the Thermal Management >> + Unit. It is used as a syscon provider for the main TMU driver. > > No, it is not a syscon provider. Entire last sentence is incorrect. You > must describe here hardware and this hardware does not provide any sort > of syscon to any sort of driver. > Indeed. I'm going to link the ACPM TMU child node with the TMU node via a "samsung,tmu-regs" property. Some concern that I have is that I describe the clocks and interrupts in the ACPM TMU child node. Usually the clocks and interrupts belong to the node that contains the reg property. But I guess that's alright because the interrupts property is expected to be in the node that the driver binds to. For the clocks, by placing it in the ACPM child node, I allow runtime PM to manage it. Do you think the below description is accurate? soc: soc@0 { tmu_top: thermal-sensor@100a0000 { compatible = "google,gs101-tmu-top"; reg = <0x100a0000 0x800>; }; }; firmware { acpm_ipc: power-management { compatible = "google,gs101-acpm-ipc"; /* ... */ thermal-sensor { compatible = "google,gs101-acpm-tmu-top"; clocks = <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; interrupts = ; samsung,tmu-regs = <&tmu_top>; #thermal-sensor-cells = <1>; }; }; }; Thanks! ta