Re: [PATCH v3] drivers/pci/intel-iommu.c: errors with smaller iommu widths

[Chris Wright <chrisw@sous-sol.org>]

* Andrew Morton (akpm@linux-foundation.org) wrote:
> On Mon, 19 Apr 2010 14:44:16 -0700
> "Tom Lyon" <pugs@cisco.com> wrote:
> > 
> > When using iommu_domain_alloc with the Intel iommu, the domain address width
> > is always initialized to 48 bits (agaw 2). __This domain->agaw value is then
> > used by pfn_to_dma_pte to (always) build a 4 level page table. __However, not
> > all systems support iommu width of 48 or 4 level page tables. __In particular,
> > the Core i5-660 and i5-670 support an address width of 36 bits (not 39!), an
> > agaw of only 1, and only 3 level page tables.
> > 
> > This version of the patch simply lops off extra levels of the page tables if
> > the agaw value of the iommu is less than what is currently allocated for the
> > domain (in intel_iommu_attach_device). If there were already allocated
> > addresses above what the new iommu can handle, EFAULT is returned.
> > 	Signed-off-by: Tom Lyon <pugs@cisco.com>
> 
> This smells like a 2.6.34 patch.  Do you agree?

I didn't think this effected in-tree code.  Tom hit this while developing
a new user of the iommu interface, whereas the current user (KVM) doesn't
trigger this.

thanks,
-chris