From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: "Kirill A. Shutemov" <kirill@shutemov.name>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Siarhei Siamashka <siarhei.siamashka@nokia.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Aaro Koskinen <aaro.koskinen@nokia.com>
Subject: Re: [PATCH] Handle instruction cache maintenance fault properly
Date: Mon, 10 May 2010 14:15:20 +0100 [thread overview]
Message-ID: <20100510131519.GB7796@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <AANLkTikIbI6hKoYSZlo6QDlyi2Qjxg287i-ilHpz1FF9@mail.gmail.com>
On Mon, May 10, 2010 at 04:07:57PM +0300, Kirill A. Shutemov wrote:
> Between "clean D line..." and "invalidate I line" operations in
> v7_coherent_user_range(), the memory page may get swapped out.
> And the fault on "invalidate I line" could not be properly handled
> causing the oops.
You have to be very careful when doing this kind of change - you need to
review the behaviour of previous ARMs to ensure that you don't throw the
CPU into an infinite loop when an "external abort on linefetch" occurs.
With older CPUs, an "external abort on linefetch" is most probably fatal
to the process and can never be recovered.
next prev parent reply other threads:[~2010-05-10 13:15 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-05-10 13:07 Kirill A. Shutemov
2010-05-10 13:15 ` Russell King - ARM Linux [this message]
2010-05-10 13:34 ` Kirill A. Shutemov
2010-05-10 14:52 ` Valdis.Kletnieks
2010-05-10 14:54 ` Catalin Marinas
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